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參數(shù)資料
| 型號(hào)： | MC916X1CTH16B1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 16.78 MHz, MICROCONTROLLER, PQFP120 |
| 封裝： | QFP-120 |
| 文件頁(yè)數(shù)： | 14/172頁(yè) |
| 文件大小： | 1200K |
| 代理商： | MC916X1CTH16B1 |
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MOTOROLA
MC68HC916X1
110
MC68HC916X1TS/D
DTL[7:0] — Length of Delay after Transfer
When the DT bit in command RAM is set, this field determines the length of delay after serial transfer.
The following equation is used to calculate the delay:
where DTL equals {1, 2, 3,..., 255}.
A zero value for DTL[7:0] causes a delay-after-transfer value of 8192/System Clock.
If DT equals zero, a standard delay is inserted.
Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted
between consecutive transfers to allow serial A/D converters to complete conversion.
SPCR2 contains QSPI configuration parameters. The CPU can read and write this register; the
QSM has read access only. Writes to SPCR2 are buffered. A write to SPCR2 that changes a bit
value while the QSPI is operating is ineffective on the current serial transfer, but becomes effective
on the next serial transfer. Reads of SPCR2 return the current value of the register, not of the buffer.
SPIFIE — SPI Finished Interrupt Enable
0 = QSPI interrupts disabled
1 = QSPI interrupts enabled
SPIFIE enables the QSPI to generate a CPU interrupt upon assertion of the status flag SPIF.
WREN — Wrap Enable
0 = Wraparound mode disabled
1 = Wraparound mode enabled
WREN enables or disables wraparound mode.
WRTO — Wrap To
When wraparound mode is enabled, after the end of queue has been reached, WRTO determines
which address the QSPI executes.
Bit 12 — Not Implemented
ENDQP[3:0] — Ending Queue Pointer
This field contains the last QSPI queue address.
Bits [7:4] — Not Implemented
NEWQP[3:0] — New Queue Pointer Value
This field contains the first QSPI queue address.
SPCR2 — QSPI Control Register 2
$YFFC1C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SPIFIE WREN WRTO
0
ENDQP[3:0]
0
NEWQP[3:0]
RESET:
0
Delay after Transfer
32
DTL[7:0]
×
System Clock
------------------------------------
=
Standard Delay after Transfer
17
System Clock
------------------------------------
=
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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