
MOTOROLA
MC68HC916X1
130
MC68HC916X1TS/D
10. If the location is programmed, repeat the same number of pulses as required to program
the location. This provides 100% program margin.
11. Read the address to verify that it remains programmed.
12. Clear the LAT bit in FEExCTL. This disables the programming address and data latches.
13. If more locations are to be programmed, repeat steps 2 through 10.
14. Reduce voltage applied to the VFPE pin to normal read level.
9.6.4.2 Erasure
The following steps are used to erase a flash EEPROM array. Figure 23 is a flowchart of the era-
 tionships during erasure.
1.
Increase voltage applied to the VFPE pin to program/erase/verify level.
2.
Set the ERAS bit and the LAT bit in FEExCTL. This configures the module for erasure.
3.
Perform a write to any valid address in the control block or array. The data written does not
matter.
4.
Set the ENPE bit in FEExCTL. This applies the erase voltage to the array.
5.
Delay the proper amount of time for one erase pulse. Delay is specified by parameter tepk.
6.
Clear the ENPE bit in FEExCTL. This turns off erase voltage to the array.
7.
Delay while high voltage to array is turned off. Delay is specified by parameter ter.
8.
Read the entire array and control block to ensure all locations are erased.
9.
If all locations are not erased, calculate a new value for tepk (tei × pulse number) and repeat
steps 3 through 10 until all locations erase, or the maximum number of pulses has been
applied.
10. If all locations are erased, calculate the erase margin (em) and repeat steps 3 through 10
for the single margin pulse.
11. Clear the LAT and ERAS bits in FEExCTL. This allows normal access to the flash.
12. Reduce voltage applied to the VFPE pin to normal read level.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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