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參數(shù)資料
| 型號(hào)： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁(yè)數(shù)： | 90/152頁(yè) |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Interrupts
MC68HC05L25 Data Sheet, Rev. 3.1
42
Freescale Semiconductor
An RTI instruction is used to signify when the interrupt software service routine is completed. The RTI
instruction causes the register contents to be recovered from the stack and normal processing to resume
at the next instruction that was to be executed when the interrupt took place. Figure 6-1 shows the
sequence of events that occurs during interrupt processing.
6.3 Reset Interrupt Sequence
The reset function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner
as shown in Figure 6-1. A low level input on the RESET pin or internally generated RST signal causes the
program to vector to its starting address, which is specified by the contents of memory locations $1FFE
through $1FFF. The I bit in the condition code register also is set. The MCU is configured to a known state
during this type of reset as previously described in Chapter 5 Resets.
6.4 Software Interrupt (SWI)
The SWI is an executable instruction and a nonmaskable interrupt since it is executed regardless of the
state of the I bit in the CCR. If the I bit is zero (interrupts enabled), the SWI instruction executes after
interrupts which were pending before the SWI was fetched or before interrupts generated after the SWI
was fetched. The interrupt service routine address is specified by the contents of memory locations
$1FFC and $1FFD.
6.5 Hardware Interrupts
All hardware interrupts except reset are maskable by the I bit in the CCR. If the I bit is set, all hardware
interrupts (internal and external) are disabled. Clearing the I bit enables the hardware interrupts. Two
types of hardware interrupts are explained in the following sections.
6.6 External Interrupt (IRQ)
The IRQ pin provides an asynchronous interrupt to the CPU. The IRQ pin is enabled by the IRQE bit in
the INTCR. Also see 7.4 Port C. The interrupt service routine address is specified by the contents of
memory locations $1FFA:$1FFB.
CPU instructions BIH and BIL test the pin state of the PC3/IRQ pin.
6.6.1 External Interrupt Trigger Condition
External interrupt (IRQ) is activated by the negative-edged signal.
The limit on the minimum pulse width (tILIH) is as specified. The pulse interval (tILIL) must be longer than
the interrupt service routine's service time + 21 machine cycles.
H
L
PC3/IRQ
tILIH
tILIL
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