參數(shù)資料
型號： MC68HC05L25PB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52
封裝： TQFP-52
文件頁數(shù)： 147/152頁
文件大?。?/td> 897K
代理商： MC68HC05L25PB
Serial Peripheral Interface
MC68HC05L25 Data Sheet, Rev. 3.1
94
Freescale Semiconductor
10.5 Register Description
The SPI has three registers: control register (SPCR), status register (SPSR), and data register (SPDR).
SPCR and SPDR can be read or written by the CPU, but SPSR can only be read.
10.5.1 Serial Peripheral Control Register
SPIE — SPI Interrupt Enable
When SPIE (SPI interrupt enable) is set, it allows the occurrence of processor interrupt when SPIF in
the SPSR is set. This interrupt request is accepted when the I bit in the CCR is cleared but inhibited
when I bit is set. If the interrupt request is sent repeatedly while the I bit and only when SPIE and SPIF
are set, the interrupt will occur immediately after the I bit is cleared. Reset clears this bit.
1 = SPI interrupt enabled
0 = SPI interrupt disabled
SPE — SPI Enable
When SPE (SPI enable) is set, it enables the SPI system and connects bit 0 and bit 1 of port C to SCK
and SDIO. Clearing SPE initializes the SPI system and disconnects SPI from port C. Reset clears this
bit.
1 = SPI enabled
0 = SPI disabled
NOTE
PC0/SCK should be at VDD level before SPI is enabled. This can be done
with an internal or external pullup resistor or by setting DDRC0 = 1 and PC0
= 1 prior to enabling the SPI. Otherwise, the circuit will not initialize
correctly.
DORD — Data Transmission Order
When DORD is set, the data in the 8-bit shift register (SPDR) is shifted in/out from LSB first. When
clear, the data is shifted MSB first. Reset clears this bit.
1 = LSB first
0 = MSB first
MSTR — Master Mode Select
This MSTR (master mode select) bit determines whether to output the serial clock internally or input
the clock externally. When set, SPI is in master mode and SCK is configured as an output pin. SCK
outputs the serial clock when CPU writes data to SPDR. When cleared, the SPI is in slave mode and
SCK is configured as an input pin. SCK receives the serial clock externally. Reset clears this bit.
1 = Master mode
0 = Slave mode
Address:
$000A
Bit 7
654321
Bit 0
Read:
SPIE
SPE
DORD
MSTR
000
SPR
Write:
Reset:
00000000
= Unimplemented
Figure 10-2. SPI Control Register (SPCR)
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