參數(shù)資料
型號: MC68HC05L25PB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52
封裝: TQFP-52
文件頁數(shù): 118/152頁
文件大小: 897K
代理商: MC68HC05L25PB
Input/Output Ports (I/O)
MC68HC05L25 Data Sheet, Rev. 3.1
68
Freescale Semiconductor
7.4.1 Port C Data Register
Each port C input pin has a corresponding bit in the port C data register. Regardless of the peripheral
configuration, any read of the port C data register will return the logic state of the corresponding I/O pin.
The port C data register is unaffected by reset.
7.4.2 Port C Data Direction Register
Each port C I/O pin can be programmed as an input by clearing the corresponding bit in the DDRC or
programmed as an output by setting the corresponding bit in the DDRC. The DDRC can be accessed at
address $0002 of the option map. The DDRC is cleared by reset.
7.4.3 Port C Pullup Register
Each port C pin can have a software programmable pullup device enabled by the RCR2 select bit RC.
The pullup is activated whenever the RC bit in the RCR2 is set. Since reset clears the RCR2, all pins will
initialize with the pullup devices disabled. See 7.5.7 Resistor Control Register 2.
7.4.4 Port C Wired-OR Mode Register
Port C bits 0 and 1 are configured for output pins and can have software programmable wired-OR mode
(open drain) output enabled by the CWOM bit in the WOMR. Since reset clears the WOMR, the wired-OR
mode is disabled on reset. Port C bits 2 and 3, when configured as an output port, have wired-OR mode
7.4.5 I/O Pin Truth Tables
Table 7-9 through Table 7-12 summarize the input, pullup, wired-OR mode, and SPI pin programming.
Address:
$0002
Bit 7
654321
Bit 0
Read:
0000
PC3PC2
PC1PC0
Write:
Reset:
0000
UUUU
= Unimplemented
U = Unaffected
Figure 7-17. Port C Data Register (PORTC)
Address:
Option — $0002
Bit 7
654321
Bit 0
Read:
0000
DDRC3
DDRC2
DDRC1
DDRC0
Write:
Reset:
00000000
= Unimplemented
Figure 7-18. Port C Data Direction Register (DDRC)
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