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參數(shù)資料
| 型號(hào)： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁(yè)數(shù)： | 146/152頁(yè) |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Functional Description
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
93
10.3.8 Serial Data In (SDI)
The SDI pin is multiplexed with a general-purpose I/O pin. This becomes an input-only pin and accepts
serial input data when the SPI is enabled.
10.3.9 Serial Clock (SCK)
The SCK pin is used for synchronization of both input and output data streams through SDI and SDO pins.
The SCK pin should be at VDD level before SPI is enabled.
The master and slave devices are capable of exchanging a data byte during a sequence of eight clock
pulses. Since SCK is generated by the master, slave data transfer is accomplished by synchronization of
SCK.
When the MSTR bit in the SPCR is set, SCK becomes an output and the serial clock is supplied to the
internal and external systems. When the serial clock is idling, high level is being output. When the bit is a
logic 1, the CPU writes data to SPCR and outputs eight clock pulses. After the end of the eighth clock,
high level is being output while idling. The clock speed in master mode is one-half the system clock.
When the MSTR bit in the SPCR is cleared, SCK becomes an input and the external system supplies the
serial clock while the internal system operates by synchronizing to this clock. After eight serial clocks are
input to the SCK pin, the SPIF bit in the SPSR is set and will not receive the next serial clock input until
the SPIF bit is cleared. The clock speed in slave mode is dependent upon the speed of the external
system and has a maximum speed up till the internal system clock.
10.4 Functional Description
A block diagram of the SPI module is shown in Figure 10-1. In the SPI, if the SPE bit (SPI enable) of SPCR
is set, bits 0, 1, and 2 of port C will be connected. During this time, bit 0 is used as the SCK (serial clock),
bit 1 as the SDO (serial data out), and bit 2 will become SDI. When SPE is a logic zero, SPI system is
disabled.
In master mode (MSTR = 1), SCK becomes an output. When the CPU writes data to SPDR, start trigger
will be applied from the control logic to the clock generator. The clock generator divides the system clock
of the CPU (by 2 or 16) to generate the serial clock which is then output to the SCK pin. This clock is also
used in the 3-bit clock counter and 8-bit shift register (SPDR).
In slave mode (MSTR = 0), SCK becomes an input, and the external serial clock is used. Therefore, the
internal clock generator will not generate the serial clock. After detecting the external clock, the clock will
be used by the 3-bit clock counter and the 8-bit shift register (SPDR) located in the clock generator. The
SCK is used to latch incoming data.
In either master or slave mode, the SPIF flag is set after the end of the transmission and if the SPIE bit in
the SPCR is set, the interrupt request is sent to the CPU. This interrupt request is accepted when the I
mask bit of condition code register (CCR) is a logic zero and is inhibited when the bit is a logic one or until
the mask is released. Also, if the SPIE bit is cleared, the interrupt request will not be accepted by the CPU.
To clear the SPIF while it is still set, the SPDR must be read or written after accessing SPSR.
Regardless of the master/slave I/O conditions, the DCOL bit of SPSR will be set when SPDR is accessed
while the shift register is operating and while SPSR is not being accessed with SPIF set. DCOL is used
to indicate that the data is not being properly read or written into SPDR.
To clear the DCOL flag while it is still set, the SPDR must be read or written after accessing SPSR.
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