參數(shù)資料
型號: MC68HC05L25PB
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52
封裝: TQFP-52
文件頁數(shù): 132/152頁
文件大小: 897K
代理商: MC68HC05L25PB
Oscillators and Clock
MC68HC05L25 Data Sheet, Rev. 3.1
80
Freescale Semiconductor
8.10 XOSC
The oscillator (XOSC) runs continuously after power-up. The XOSC never stops while power is applied.
XOSC pins have options for feedback and damping resistor implementations. These options are set
through mask option and may be read through the mask option status register (MOSR). See 1.3 Mask
8.11 Stop and Wait Modes
Power reduction can be achieved by executing the STOP instruction and halting the CPU. During stop
mode, the CPU and all modules except time base are halted. The stop mode is exited by external RESET,
COP reset, IRQ, SPI (slave mode), or TB interrupt. The CPU resumes immediately from stop mode since
XOSC never stops oscillating during stop mode.
The CPU clock is halted and the peripheral modules are not affected during wait mode. Wait mode is
exited by RESET or any interrupts.
8.12 Miscellaneous Register
FTUP — OSC Time Up Flag
Power-on detection and clearing FOSCE bit clears this bit. This bit is set by the overflow of the POR
counter. A reset does not affect this bit.
Read:
1 = OSC clock available for the system clock
0 = During POR or OSC shut down
Table 8-3. Recovery Time Requirements
Mode Before
Reset or Interrupt
Delay Time After Reset or Interrupt
Power-On Reset
COP and
External RESET
Exit Stop Mode
by Interrupt
Power Off
Delay
Run
See Note
No Delay
Stop/Wait
See Note
No Delay
NOTE: Power-on reset is strictly for power-on conditions and does not detect a drop in power.
Address:
$003E
Bit 7
654321
Bit 0
Read:
FTUP
STUP
0
SYS1
SYS0
FOSCE
OPTM
Write:
Reset:
U
000010
= Unimplemented
U = Unaffected
Figure 8-4. Miscellaneous Register (MISC)
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