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參數(shù)資料
| 型號： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 84/152頁 |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Registers
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
37
Interrupt Mask (I Bit)
When the I bit is set, the internal and external interrupts are disabled. Interrupts are enabled when the
interrupt mask is cleared. When an interrupt occurs, the interrupt mask is set automatically after the
CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request
occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is
processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt
mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and
can be cleared only by the clear I bit (CLI), STOP, or WAIT instructions.
Negative Bit (N Bit)
The N bit is set when the result of the last arithmetic operation, logical operation, or data manipulation
was negative. (Bit 7 of the result was a logical 1.)
The negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a
register or memory location. Loading the accumulator with the contents of that register or location then
sets or clears the negative bit according to the state of the flag.
Zero Bit (Z Bit)
The Z bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or
data load operation was zero.
Carry/Borrow Bit (C Bit)
The C bit is set when a carry out of accumulator bit 7 occurs during the last arithmetic operation, logical
operation, or data manipulation. The carry/borrow bit also is set or cleared during bit test and branch
instructions and during shifts and rotates. This bit is not set by an INC or DEC instruction.
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