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參數(shù)資料
| 型號： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 78/152頁 |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
31
Chapter 3
Operating Modes
3.1 Introduction
The MC68HC05L25 has three modes of operation that affect the pinout and architecture of the MCU:
single-chip mode, internal test mode, and expanded test mode. The single-chip mode normally will be
used, while the test modes are required for the special needs of production test and burn-in.
3.2 Single-Chip Mode
Single-chip mode allows the MCU to function as a self-contained microcontroller with maximum use of
the pins for on-chip peripheral functions. The pinout for the single-chip mode is shown in Figure 1-2 and
In single-chip mode, all address and data activity occurs within the MCU and is not available externally.
3.3 Low-Power Modes
In each of its configuration modes, the MC68HC05L25 is capable of running in one of two low-power
operational modes. The WAIT and STOP instructions provide two modes that reduce the power required
for the MCU by stopping various internal clocks and/or the on-chip oscillator. The STOP and WAIT
instructions are not normally used if the COP watchdog timer is enabled. The flow of the stop and wait
modes is shown in Figure 3-1.
3.3.1 STOP Instruction
Execution of the STOP instruction places the MCU in its lowest power-consumption mode. In stop mode,
the internal oscillator is turned off, halting all internal processing except the time base/COP watchdog
timer, if it is enabled and clocked from XOSC.
Execution of the STOP instruction automatically clears the I bit in the condition code register. All other
registers and memory remain unaltered. All input/output lines remain unchanged. Therefore, unused
ports must be programmed as output or tied to the power rails to prevent excessive current consumption.
The MCU can be brought out of stop mode by an external IRQ interrupt, KWI interrupt, SPI (slave mode
only) interrupt or TBI interrupt clocked by XOSC or a reset.
3.3.2 WAIT Instruction
The WAIT instruction places the MCU in a low-power mode, which consumes more power than stop
mode. In wait mode, the internal processor clock is halted, suspending all processor and internal bus
activity. Internal timer clocks remain active, permitting interrupts to be generated from the timer or a reset
to be generated from the COP watchdog timer. Execution of the WAIT instruction automatically clears the
I bit in the condition code register and external interrupt is allowed. All other registers, memory, and
input/output lines remain in their previous states.
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