參數(shù)資料
型號： MC68HC05L25PB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52
封裝： TQFP-52
文件頁數(shù)： 122/152頁
文件大小： 897K
代理商： MC68HC05L25PB
I/O Port Programming
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
71
7.5 I/O Port Programming
All bidirectional I/O pins can be programmed as inputs or outputs.
7.5.1 Pin Data Direction
The direction of a pin is determined by the state of its corresponding bit in the associated port data
direction register (DDR). A pin is configured as an output if its corresponding DDR bit is set to a logic 1.
A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0.
The data direction bits DDRA0:DDRA7, DDRB0:DDRB7, and DDRC0:DDRC3 are read/write bits which
can be manipulated with read-modify-write instructions. At power-on or reset, all DDRs are cleared, which
configures all I/O port pins as input (except port B is configured as an LCD port).
7.5.2 Output Pin
When an I/O pin is programmed as an output pin, the state of the corresponding data register bit will
determine the state of the pin. The state of the data register bits can be altered by writing to address $0000
for port A, address $0001 for port B, and address $0002 for port C. Reads of the corresponding data
register bit at address $0000 or $0003 will return the state of the data register bit (not the state of the I/O
pin itself). Therefore, bit manipulation is possible on all pins programmed as outputs.
7.5.3 Input Pin
When an I/O pin is programmed as an input pin, or for an input-only pin, the state of the pin can be
determined by reading the corresponding data register bit. Any writes to the corresponding data register
bit for an input-only pin will be ignored.
If the corresponding bit in the pullup register is set, the input pin will have an activated pullup device. Since
the pullup register bits are read-write, bit manipulation may be used on these register bits.
Table 7-12. PC3/IRQ I/O Pin Functions
DDR
Output
Latch
INTCR
IRQE
WOMR
CWOM
RCR2
RC Bit
I/O Pin Modes
Access to
DDRC3
Access to Data Register
Latch PC3
Read/Write
Read
Write
0
X
0
X
0
Port IN, Hi-Z
DDRC3
Pin
Latch2
0
X
0
X
1
Port IN, Pullup
DDRC3
Pin
Latch2
0
X
1
X
0
Port IN, Hi-Z, IRQ
DDRC3
Pin
Latch2
0
X
1
X
1
Port IN, Pullup, IRQ
DDRC3
Pin
Latch2
1
0
X
Port OUT, OD
DDRC3
Latch
Latch, Pin
1
0
X
0
Port OUT, OD, Hi-Z
DDRC3
Latch
Latch, Pin
1
0
X
1
Port OUT, OD, Pullup
DDRC3
Latch
Latch, Pin
1
0
1
X
Port OUT, OD, IRQ
DDRC3
Latch
Latch, Pin
1
X
0
Port OUT, OD, Hi-Z, IRQ
DDRC3
Latch
Latch, Pin
1
X
1
Port OUT, OD, Pullup, IRQ
DDRC3
Latch
Latch, Pin
1. X is don’t care state.
2. Does not affect input, but stored to data register latch
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