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參數(shù)資料
| 型號： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 4/152頁 |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Functional Description
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
101
11.3.2 Fast Change Option
The RLCD is approximately 160 k at VDD = 3 V by default. This value can be inappropriate for some
applications. For those applications that require less DC current drain through the RLCD chain, it may be
increased to approximately 860 k
at VDD = 3 V by setting the LC bit in LCDCR. Some applications may
require the default resistance to drive the capacitive load of the LCD panel, yet do not wish to have the
DC current drain of it while the LCD segments are not switching. For a compromise, a fast-charge option
is available. The RLCD values are reduced to the default resistance for a fraction of the LCD segment cycle
before the LCD segments change, and then are set to low-current mode for the remainder of the LCD
cycle frame. The DC current increase is very negligible and will be within a few percent increase of the
low-current mode.
Figure 11-3. BP0/FC Clock Timing
11.3.3 LCD Data Registers
The LCD data latches LDAT1 through LDAT11 maintain the ON/OFF data for the FP and BP segments
of the LCD.
Four bits of data latch are assigned to each frontplane driver from address space $21 through $2D as
shown in Figure 11-4.
When a logic 1 is written to the bits in the data latch, the applicable FP-BP segment turns ON. When a
logic 0 is written to the bits, the segment is turned OFF.
The values in the data latches are not initialized and are unknown on reset.
If 1/3 duty is selected, each BP3 bit in the data latches is ignored.
Table 11-1. RLCD Configuration
FC
LC
Action
X
0
Default value of approximately 160 k
per resistor
0
1
Resistor value of approximately 860 k
per resistor
11
Fast-Charge: For a period of LCDCLK/128 in each frame, the resistor values
are reduced to default (value for LC = 0).
BP0
FC CLOCK
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