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| 型號： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 129/152頁 |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Oscillators and Clock
MC68HC05L25 Data Sheet, Rev. 3.1
78
Freescale Semiconductor
8.7 Stop and Wait Modes
During stop mode, the main oscillator (OSC) is shut down and the clock path from the second oscillator
(XOSC) is disconnected, such that all modules except time base are halted. Entering stop mode clears
the FTUP flag in the MISC register and initializes the POR counter. Stop mode is exited by RESET, IRQ,
KWI, SPI (slave mode), or TBI interrupt.
If OSC is selected as the system clock source during stop mode, CPU resumes after the overflow of the
POR counter, and this overflow also sets FTUP status flag.
If XOSC is selected as the system clock source during stop mode, no stop recovery time is required for
exiting stop mode because XOSC never stops, and re-start of main oscillator depends on FOSCE bit.
During wait mode, only the CPU clocks are halted and the peripheral modules are not affected. Wait mode
is exited by the RESET and any interrupts.
NOTE
Power-on reset is strictly for power-on conditions and does not detect a
drop in power.
8.8 XOSC Clock Divider and POD Counter
The XOSC clock divided by a 14-bit counter, also called power-on divider (POD), is used for the system
clock. The oscillator clock divided by two is used by the system clock and oscillator clock divided by 64
or 128 is provided for the LCD module.
The overflow of the POD counter is used for setting the STUP bit and releasing power-on reset (POR).
The 14-bit divider/POD counter is initialized to $0078 by power-on detection.
8.9 System Clock Control
The system clock (PH2) is provided for CPU and all internal modules.
Table 8-2. CPU Startup Time Requirements
Before RESET or Interrupt
Power-On
Reset
External
RESET
Exit Stop Mode
by an Interrupt
CPU Clock Source
CPU
FOSCE
——
—
Delay
—
OSC (OSC ON)
RUN
1
—
No Delay
—
OSC (OSC OFF)
RUN
01
—Delay
—
STOP
1
—
Delay
STOP
02
—Delay
Delay
XOSC (OSC ON)
RUN
1
—
No Delay
—
XOSC (OSC OFF)
RUN
0
—
Delay
—
STOP
1
—
Delay
No Delay
STOP
0
—
Delay
No Delay
1. Do not enter this state.
2. This state does not exist.
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