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參數(shù)資料
| 型號： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 18/152頁 |
| 文件大小： | 897K |
| 代理商： | MC68HC05L25PB |
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Analog Subsystem
MC68HC05L25 Data Sheet, Rev. 3.1
114
Freescale Semiconductor
12.5.1 Conversion Times
Each input conversion requires 32 PH2 (bus) clock cycles, which must be at a frequency equal to or
greater than 1 MHz.
12.5.2 Internal versus External Oscillator
If the MCU PH2 clock frequency is less than 1 MHz (2-MHz external oscillator), the internal RC oscillator
(approximately 1.5 MHz) must be used for the A/D converter clock. The internal RC clock is selected by
setting the ADRC bit in the ADSC register.
When the internal RC oscillator is being used, these limitations apply:
1.
Since the internal RC oscillator is running asynchronously with respect to the PH2 clock, the
conversion complete bit (CC) in register ADSC must be used to determine when a conversion
sequence has been completed.
2.
Electrical noise will slightly degrade the accuracy of the A/D converter. The A/D converter is
synchronized to read voltages during the quiet period of the clock driving it. Since the internal and
external clocks are not synchronized, the A/D converter occasionally will measure an input when
the external clock is making a transition.
3.
If the PH2 clock is 1 MHz or greater (for example, external oscillator 2 MHz or greater and
SYS1–SYS0 = 0–0), the internal RC oscillator must be turned off and the external oscillator used
as the conversion clock.
12.5.3 Multi-Channel Operation
An input multiplexer allows the A/D converter to select from one of two external analog signals. Port A
pins PA4 and PA5 are shared with the inputs to the multiplexer.
NOTE
Applying analog voltage to an A/D input pin that is not selected (used as a
general-purpose digital I/O port) may result in excessive IDD.
12.6 A/D Subsystem Operation during Wait Modes
The A/D subsystem continues normal operation during wait modes. To decrease power consumption
during wait, the ADON and ADRC bits in the A/D status and control register should be cleared if the A/D
subsystem is not being used.
12.7 A/D Subsystem Operation during Stop Modes
When stop mode is enabled, execution of the STOP instruction will terminate all A/D subsystem functions.
Any pending conversion is aborted. When the oscillator resumes operation upon leaving stop mode, a
finite amount of time passes before the A/D subsystem stabilizes sufficiently to provide conversions at its
rated accuracy. The delays built into the MC68HC05L25 when coming out of stop mode are sufficient for
this purpose. No explicit delays need to be added to the application software.
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