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| 型號： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁數(shù)： | 26/152頁 |
| 文件大?。?/td> | 897K |
| 代理商： | MC68HC05L25PB |
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Event Counter Interrupts
MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
121
on the fourth internal processor clock cycle of the write to the event counter timing register. The event
counter data registers are cleared on the rising edge of the internal gate signal. The external gate signal
rises two clock cycles later.
After MT3–MT0 x tgt, the gate signal will rise, terminating the measurement time. The gate signal will be
the same length for all successive measurements.
Unless the start of the gate delay signal and the event counter input signal are externally synchronized,
the value of the least significant bit of the event counter data low register may arbitrarily change.
If the fast oscillator, OSC, is disabled, the event counter will not function properly.
13.5 Event Counter Interrupts
The event counter complete interrupt (ECCI) is generated at the falling edge of the gate signal. This
interrupt indicates the presence of valid data in the event counter data registers. Since reading the data
registers during the measurement time may give invalid results, the CPU must read the data registers
before the rising edge of the gate signal. The event counter complete interrupt can be cleared by writing
a one to RCCF. The event counter complete interrupt is cleared automatically at the beginning of each
measurement.
The event counter overflow interrupt (EVOF) is generated if the count exceeds 65,535, the maximum
value of the 16-bit event counter. This interrupt can be used to indicate an invalid measurement or to
increase the resolution of the event counter, which will be described later. The event counter overflow
interrupt can be cleared by writing a one to ROIF. The event counter overflow interrupt is cleared
automatically at the beginning of each measurement.
If an overflow occurs (the counter increments beyond $FFFF), the event counter overflow flag (EVOF) will
be set. If EVOE is set, an interrupt will be generated. Following an overflow, the event counter will
increment from zero.
The resolution of the event counter can be increased by using the event counter overflow interrupt. If it is
a count of more than 65,535 the maximum value of the 16-bit event counter is encountered, the event
counter overflow interrupt service routine should note the number of “roll-overs” that occur. The overflow
interrupt service routine should not clear the event counter interrupt. In this way, the user can be assured
that the correct count has been recorded.
13.6 Event Counter During Wait Mode
The event counter continues to operate in wait mode. If EVOE is set and an event counter overflow
interrupt occurs, the processor will exit wait mode. If EVIE is set and an event counter interrupt occurs,
the processor will exit wait mode.
13.7 Event Counter During Stop Mode
In stop mode, the event counter is disabled.
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