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參數(shù)資料
| 型號(hào)： | MC68HC05L25PB |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PQFP52 |
| 封裝： | TQFP-52 |
| 文件頁(yè)數(shù)： | 86/152頁(yè) |
| 文件大小： | 897K |
| 代理商： | MC68HC05L25PB |
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MC68HC05L25 Data Sheet, Rev. 3.1
Freescale Semiconductor
39
Chapter 5
Resets
5.1 Introduction
The MCU can be reset from three sources: one external input and two internal restart conditions. The
RESET pin is an input with a Schmitt trigger as shown in Figure 5-1. All peripheral modules which drive
external pins will be reset by the synchronous reset signal (RST) coming from a latch, which is
synchronized to the PH2 bus clock and set by any of the three reset sources.
Figure 5-1. Reset Block Diagram
5.2 External Reset (RESET)
The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate
to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This
external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset
until the RESET pin rises above the upper threshold. This active low input will generate the RST signal
and reset the CPU and peripherals. Termination of the external RESET input or the internal COP
watchdog reset are the only reset sources that can alter the operating mode of the MCU.
NOTE
Activation of the RST signal generally is referred to as reset of the device,
unless otherwise specified.
5.3 Internal Resets
The two internally generated resets are the initial power-on delay function and the COP watchdog timer
reset. Termination of the external RESET input or the internal COP watchdog timer are the only reset
sources that can alter the operating mode of the MCU. The other internal resets will not have any effect
on the mode of operation when their reset state ends.
CPU
LATCH
RESET
COP WATCHDOG
(COPR)
RST
OSC
DATA
ADDRESS
PH2
TO OTHER
PERIPHERALS
S
POWER-ON DELAY
(POD)
VDD
PH2 IS AN INTERNAL BUS
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