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參數(shù)資料
| 型號： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 99/124頁 |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MOTOROLA
8-10
MC68HC05G1
SERIAL PERIPHERAL INTERFACE
8
8.4.2
Serial Peripheral Status Register (SPSR)
This is a read-only register. The status ags which generate a serial peripheral interface (SPI)
interrupt may be blocked by the SPIE control bit in the serial peripheral control register. The WCOL
bit does not cause an interrupt. The serial peripheral status register bits are dened as follows:
8.4.2.1
SPIF - Serial Peripheral Data Transfer Complete Flag
The serial peripheral data transfer ag bit noties the user that a data transfer between the device
and an external device has been completed. With the completion of the data transfer, SPIF is set,
and if SPIE is set, a serial peripheral interrupt is generated. During the clock cycle that SPIF is
being set, a copy of the received data byte in the shift register is moved to a buffer. When the data
register is read, it is the buffer that is read. During an overrun condition, when the master device
has sent several bytes of data and the slave device has not responded to the rst SPIF, only the
rst byte sent is contained in the receiver buffer and all other bytes are lost.
The transfer of data is initiated by the master device writing its serial peripheral data register.
Clearing the SPIF bit is accomplished by a software sequence of accessing the serial peripheral
status register while SPIF is set and followed by a write to or a read of the serial peripheral data
register. While SPIF is set, all writes to the serial peripheral data register are inhibited until the
serial peripheral status register is read. This occurs in the master device. In the slave device, SPIF
can be cleared (using a similar sequence) during a second transmission; however, it must be
cleared before the second SPIF in order to prevent an overrun condition. The SPIF bit is cleared
by reset.
8.4.2.2
WCOL - Write Collision Status
The function of the write collision status bit is to notify the user that an attempt was made to write
to the serial peripheral data register while a data transfer was taking place with an external device.
The transfer continues uninterrupted; therefore, a write will be unsuccessful. A “read collision” will
never occur since the received data byte is placed in a buffer in which access is always
synchronous with the MCU operation. If a “write collision” occurs, WCOL is set but no SPI interrupt
is generated. The WCOL is a status ag only.
Clearing the WCOL bit is accomplished by a software sequence of accessing the serial peripheral
status register while WCOL is set, followed by 1), a read if the serial peripheral data register prior
to the SPIF bit being set, or 2) a read or write of the serial peripheral data register after the SPIF
bit is set. A write to the serial peripheral data register (SPDR) prior to the SPIF bit being set, will
result in generation of another WCOL status ag. Both the SPIF and WCOL bits will be cleared in
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$2B
SPIF
WCOL
MODF
00-0 ----
TPG
72
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