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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 63/124頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
5-9
INTERRUPTS
5
ICF - Input Capture Flag
ICF is set when a proper edge has been sensed by the input capture edge
detector. It is cleared by an CPU read of the TSR (with ICF set) followed by
accessing the Input Capture Register least signicant byte ($15). Reset does not
affect this bit.
All three timer interrupt ags have corresponding enable bits (ICIE, OCIE, and TOIE) found in the
Timer Control Register (TCR) at location $12. Reset clears all enable bits preventing an interrupt
from occurring. The actual processor interrupt is generated only if the interrupt mask bit of the
Condition Code register is also cleared. When the interrupt is recognized, the current state of the
machine is pushed onto the stack and the interrupt mask bit in the Condition Code register is set.
This masks further interrupts until the present one is serviced. The service routine address is
specied by the contents of $3FF6 and $3FF7.
Refer to section 7 - Programmable Timer for detailed description.
5.7
RTC Interrupt
An RTC interrupt is enabled when either the RTCE, ALE or SECE bit in the RTC Control register
($1D) is set, provided the interrupt mask bit in the Condition Code register is cleared. When RTCE
bit is set, real time clock will interrupt the CPU once a day. This will occur when the hours register
in real time clock register changes from twenty-three to zero. When the SECE bit is set, the real
time clock will interrupt CPU once a second. When ALE bit is set, RTC interrupt will occur when
the value of hour alarm and hours are equal, and the value of minute alarm and minutes are equal.
When the interrupt is recognized, the current state of the machine is pushed onto the stack and
the interrupt mask bit in the Condition Code register is set. This mask further interrupts until the
present one is serviced. The interrupt causes the program counter to vector to $3FF2 - $3FF3 in
which is stored the service routine’s starting address. Interrupt per day, per second or alarm
interrupt can be distinguished by the RTCF, SECF and ALF ags. In order to reset the interrupt,
users are responsible for clearing the appropriate ags when executing the interrupt routine.
Notice that ALF is set as long as the values of the both hour alarm and hour, minute alarm and
minutes are qual. Therefore, users may found ALF is still set even after the MCU performs an ALF
ag clearance. To avoid the same alarm interrupt from further interrupting the MCU, users can
assign a different values to the alarm register and then ALF can be cleared as a result.
Refer to section 6.2 - Real Time Clock for detailed description.
5.8
SPI Interrupt
An interrupt in the serial peripheral interface (SPI) occurs when one of the interrupt ag in the
serial peripheral status register ($2B) is set, provided the interrupt mask bit in the Condition Code
TPG
41
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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| MC68HC05J1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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