參數(shù)資料
型號(hào)： MC68HC05G1B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁數(shù)： 95/124頁
文件大?。?/td> 732K
代理商： MC68HC05G1B
MOTOROLA
8-6
MC68HC05G1
SERIAL PERIPHERAL INTERFACE
8
8.3
Functional Description
A block diagram of the serial peripheral interface is shown in Figure 8-3. In a master conguration,
the master start logic receives an input from the CPU (in form of a write to the SPI rate generator)
and originates the serial clock (SCK) based on the internal processor clock. This clock is also used
internally to control the state controller as well as the 8-bit shift register. As a master device, data
is parallel loaded into the 8-bit shift register (from internal bus) during a write cycle and then shifted
out serially to the MOSI pin for application to the slave device(s). During a read cycle, data is
applied serially from a slave device via the MISO pin to the 8-bit shift register. After the 8-bit shift
register is loaded, its data is parallel transferred to the read buffer and then is made available to
the internal data bus during a CPU read cycle.
In a slave conguration, the slave start logic receives a logic low (from a master device) at the SS
pin and serial clock input (from the same master device) at the SCK pin. Thus, the slave is
synchronized with the master. Data from the master is received serially at the slave MOSI pin and
loads the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel transferred to
the read buffer and then is made available to the internal data bus during a CPU cycle. During a
write cycle, data is parallel loaded into the 8-bit shift register from the internal data bus and then
shifted out serially to the MISO pin for application to the master device.
Figure 8-4 illustrates the MOSI, MISO, and SCK master-slave interconnections. Note that in
Figure 8-4 the master SS pin is tied to a logic high and the slave SS pin is a logic low. Figure 8-1
provides a larger system connection for these same pins. Note that in Figure 8-1, all SS pins are
connected to a port pin of a master/slave device. In this case any of the devices can be a slave.
8.4
SPI Registers
These are three registers in the serial parallel interface which provide control, status, and data
storage functions. These registers are the serial peripheral control register (SPCR, location $2A),
serial peripheral status register (SPSR, location $2B), and serial peripheral data I/O register
(SPDR, location $2C) are described in the following paragraphs.
8.4.1
Serial Peripheral Control Register (SPCR)
The serial peripheral control register bits are denes as follows:
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$2A
SPIE
SPE
MSTR
CPOL
CPHA
SPR1
SPR0
00-0 uuuu
TPG
68
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