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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 102/124頁 |
| 文件大小： | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
8-13
SERIAL PERIPHERAL INTERFACE
8
8.5
SPI during Wait Mode
When the MCU enters the wait mode, the CPU clock is halted. All CPU action is suspended;
however, the SPI system remain active. In fact an interrupt from the SPI (in addition to a logic low
on the IRQ, INT1, INT2, RTC, or a logic low on the RESET pin or a power on reset) causes the
processor to exit the wait mode.
8.6
SPI during Stop Mode
When the processor executes the STOP instruction, the internal oscillator is turned off. This halts
all internal CPU processing, including the operation of the serial peripheral interface. The only way
for the MCU to “wake-up¨ from the stop mode is by receipt of an external interrupt (logic low on
IRQ, INT1, INT2), RTC, or the detection of a reset (logic low on RESET pin or a power-on reset).
When the MCU enters the stop mode, the baud rate generator which drives the SPI shuts down.
This essentially stops all master mode SPI operation; the master SPI is unable to transmit or
receive any data. If the STOP instruction is executed during an SPI transfer, that transfer is halted
until the MCU exits the stop mode (provided it is an exit resulting from a logic low on the IRQ, INT1,
INT2 pin, interrupt from keyboard or RTC or by the detection of a reset of logic low on reset pin or
a power on reset). If the stop mode is exited by a reset, then the appropriate control/status bits are
cleared and the SPI is disabled. If the device is in the slave mode when the STOP instruction is
executed, the slave SPI will still operate. It can still accept data and clock information in addition
to transmitting its own data back to a master device.
Since the MC68HC05 is the bus master, it internally controls the function of its MOSI and MISO
lines; thus writing data to the slave devices on the MOSI and reading data from the slave devices
on the MISO lines. The master device selects the individual slave devices by using four pins of a
parallel port to control the four SS pins of the slave devices. A slave device is selected when the
master device pulls its SS pin low. The SS pins are pulled high during reset since the master
device ports will be forced to be inputs at that time, thus disabling the slave devices. Note that the
master can enable all slaves when writing to them, but can only read from one slave at a time. This
is to prevent bus contention on the MISO line.
Example: in a one master, three slaves system, the master writes to the three slaves’ display driver
to clear a display with a single I/O operation. To ensure that proper data transmission between the
master device and a slave device, the master device may have the slave device responding with
a data byte previously sent by the master (this data byte could be inverted or at least be a byte
that is different from the last one sent by the master device). The master device will always receive
the byte back from the slave device if all MISO and MOSI lines are connected and the slave has
not written to its data I/O register. Other transmission protocols may be dened using ports for
handshake lines or data bytes with command elds.
A multi-master system may also be congured by the user. A system of this type is shown in
Figure 8-1(b). An exchange of master control could be implemented using a handshake method
TPG
75
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