參數(shù)資料
型號: MC68HC05G1B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 51/124頁
文件大?。?/td> 732K
代理商: MC68HC05G1B
MOTOROLA
4-2
MC68HC05G1
RESETS
4
4.3
COP Watchdog Reset
The COP (Computer Operating Properly) watchdog timer function is implemented on this device
by using the output of the COP counter. The minimum COP reset rates are shown in Table 4-1. If
the COP circuit times out, an internal reset is generated and the reset vector is fetched (at $3FFE
& $3FFF). Preventing a COP time-out is achieved by writing a ‘0’ to bit 0 of address $3FF0. The
COP counter has to be cleared periodically by software with a period less than COP reset rate.
COP counter will stop counting in Wait and Stop modes. Counting continues when it wakes up
from WAIT mode, and a 4064 cycle delay after waking up from Stop mode.
The watchdog counter system is controlled by the WDOG bit in the Miscellaneous Control register
(bit 0 of address $27). After power-on or external reset the watchdog system is disabled. Writing
a “1” to the WDOG bit will enable the watchdog system and the counter starts counting. Once
enabled, the watchdog system cannot be disabled by software. Writing a “0” to bit 0 of address
$3FF0 will reset watchdog counter to prevent a watchdog time-out.
Note:
The COP watchdog reset rate is 220 times the CPU clock cycle.
Table 4-1 COP Reset Rate
FS1
FS0
CPU Bus Rate
Minimum COP Reset
0
0.164MHz
6.4s
0
1
1.311MHz
800ms
1
0
0.328MHz
3.2s
1
2.622MHz
400ms
FS1 and FS0 are bits in the PLL Status and Control register.
TPG
30
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