參數(shù)資料
型號(hào): MC68HC05G1B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 82/124頁
文件大?。?/td> 732K
代理商: MC68HC05G1B
MOTOROLA
7-6
MC68HC05G1
PROGRAMMABLE TIMER
7
When IEDG is set, a positive-going edge on the TCAP pin will trigger a transfer of the free-running
counter value to the input capture registers. When clear, a negative-going edge triggers the
transfer.
OLVL - Output Level Voltage Latch
1 (set)
High output on TCMP pin if counter compare is true.
0 (clear) –
Low output on TCMP pin if counter compare is true.
The programmable timer may be disabled/enabled by writing to bit 4 in the Miscellaneous Control
register.
TIMI
1 (set)
Timer inhibit
0 (clear) –
Enable timer (default at reset)
7.5
Timer Status Register (TSR)
The Timer Status register ($13) contains the status bits for the above three interrupt conditions -
ICF, OCF, TOF.
Accessing the timer status register satises the rst condition required to clear the status bits. The
remaining step is to access the register corresponding to the status bit.
ICF - Input Capture Flag
1 (set)
A valid input capture has occurred.
0 (clear) –
No input capture has occurred.
This bit is set when the selected polarity of edge is detected by the input capture edge detector;
an input capture interrupt will be generated, if ICIE is set, ICF is cleared by reading the TSR and
then the Input Capture Low register ($15)
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Miscellaneous Control Register
$27
INT2N INT1N
IRQN
TIMI
WDOG
0000 ---0
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$13
ICF
OCF
TOF
uuu- ----
TPG
56
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