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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 79/124頁 |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MOTOROLA
7-4
MC68HC05G1
PROGRAMMABLE TIMER
7
The contents of the output compare register are continually compared with the contents of the
free-running counter and, if a match is found, the output compare ag (OCF) in the Timer Status
register is set; and the output level (OLVL) bit is clocked to an output level register. The output
compare register value and the output level bit should be changed after each successful
comparison to establish a new elapsed time-out. An interrupt can also accompany a successful
output compare provided the interrupt enable bit (OCIE) is set. (The free-running counter is
updated every four internal bus clock cycles.
After a processor write cycle to the output compare register containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written rst. A write made only to the LSB ($17) will not inhibit the compare
function. The processor can write to either byte of an output compare register without affecting the
other byte. The minimum time required to update the output compare registers is a function of the
program rather than the internal hardware. Because the output compare ag and output compare
register are not dened at power-on, and not affected by reset, care must be taken when initializing
output compare functions with software. The following procedure is recommended:
1) write to Output Compare register high-byte to inhibit further compares;
2) read the Timer Status register to clear OCF;
3) write to Output Compare register low-byte to enable the output compare
function.
The output level (OLVL) bit is clocked to the output level register regardless of whether the output
compare ag (OCF) is set or clear.
7.3
Input Capture Registers
–
Input Capture Register
High byte - $14, Low byte - $15
‘Input Capture’ is a technique whereby an external signal (connected to TCAP pin) is used to
trigger a read of the free-running counter. In this way it is possible to relate the timing of an external
signal to the internal counter value, and hence to elapsed time.
The two 8-bit registers that make up the 16-bit input capture register, are read-only, and are used
to latch the value of the free-running counter after the corresponding input capture edge detector
senses a valid transition. The level transition that triggers the counter transfer is dened by the
corresponding input edge bit (IEDG). Reset does not affect the contents of the input capture
register.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition. This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles.
The free-running counter contents are transferred to the input capture register on each valid signal
transition whether the input capture ag (ICF) is set or clear. The input capture register always
TPG
54
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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