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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 93/124頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MOTOROLA
8-4
MC68HC05G1
SERIAL PERIPHERAL INTERFACE
8
Note:
Both the slave device(s) and a master device must be programmed to similar timing
modes for proper data transfer.
When the master device transmits data to a slave via a MOSI line, the slave device responds by
sending data to the master device via the MISO line. This implies full duplex transmission with both
data out and data in synchronized with the same clock signal (one which is provided by the master
device). Thus the byte transmitted is replaced by the byte received and eliminates the need for
separate transmit-empty and receiver-full status bits. A single status bit (SPIF) in the serial
peripheral status register (SPSR, location $2B) is used to signify that the I/O operation is
complete.
Conguration of the MOSI pin is a function of the MSTR bit in the serial peripheral control register
(SPCR, location $2A). When a device is operating as a master, the MOSI pin is an output because
the program in rmware set the MSTR bit as a logic one.
8.2.2
Master In Slave Out (MISO)
The MISO pin is congured as an input in a master (mode) device and as an output pin in a slave
(mode) device. Data is transferred serially from a slave to a master on this line, most signicant
bit rst. The MISO pin of a slave is placed in a high-impedance state if it is not selected by a
master; i.e., its SS pin is a logic one. The timing diagram in Figure 8-2 shows the relationship
between data and serial clock (SCK). As shown in Figure 8-2, four possible timing relationships
may be chosen by using control bits CPOL and CPHA. The master device always allows data to
be applied on the MISO line a half-cycle before the serial clock edge (SCK) in order for the slave
device to latch the data.
Note:
Both the slave device(s) and a master device must be programmed to similar timing
modes for proper data transfer.
When a master device transmits data to a slave device via the MOSI line, the slave device
responds by sending data to the master device via the MISO line. This implies full duplex
transmission with both data out and data in synchronized with the same clock signal (one which
is provided by the master device). Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receiver-full status bits. A single status bit
(SPIF) in the serial peripheral status register (SPSR, location $2B) is used to signify that the I/O
operation is complete.
In the master device, the MSTR control bit in the serial peripheral control register (SPCR, location
$2A) is set to a logic one (by the program) to allow the master device to receive data on its MISO
pin. In the slave device, its MISO pin is enabled by the logic level of the SS pin; i.e., if SS=1 then
the MISO pin is placed in a high impedance state, whereas, if SS=0 the MISO pin is an output for
the slave device.
TPG
66
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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| MC68HC05J1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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