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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 42/124頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MOTOROLA
2-4
MC68HC05G1
PIN DESCRIPTIONS
2
2.3
Input/Output Programming
2.3.1
Parallel Ports
Port A, B, C, D, and port E may be programmed as an input or an output under software control.
The direction of the pins is determined by the state of corresponding bit in the Port Data Direction
register (DDR). Each 8-bit port has an associated 8-bit Data Direction register. Any port A, B, C,
D or port E pin is congured as an output if its corresponding DDR bit is set to a logic one. A pin
is congured as an input if its corresponding DDR bit is cleared to a logic zero. At power-on or
reset, all DDRs are cleared, which congure all port A, B, C, D and port E pins as inputs. The data
direction registers are capable of being written to or read by the CPU. Refer to Figure 2-3 and
Table 2-1. During the programmed output state, a read of the data register actually reads the value
of the output data latch and not the I/O pin.
2.3.2
Fixed Ports
Port F is a 4-bit xed input port that continually monitors the external pins whenever the SPI
system is disabled. During power-on reset or external reset all four bits become valid input ports
because all special function output drivers are disabled. For example, with the serial peripheral
interface (SPI) system disabled (SPE=0) PF0 through PF3 will read the state of the pin at the time
of the read operation. No data direction register is associated with the port when it is used as an
input.
Port G is a xed, input-only, 4-bit port, which can be read at any time; it reads the four analogue
inputs to the A/D converter, when it is enabled. Port G can still be read during an A/D conversion
sequence, but this may inject noise on the analogue inputs, resulting in reduced accuracy of the
A/D. Furthermore, performing a digital read of port G with levels other than VDD or VSS on the port
G pins will result in greater power dissipation during the read cycle. Note that as port G is an input
only port there is no Data Direction Register (DDR) associated with it. Also, at power-on or
external reset, the A/D converter is disabled.
Note:
It is recommended that all unused inputs should be tied to an appropriate logic level
(e.g. either VDD or VSS).
Table 2-1 I/O Pin Functions
R/W
DDR
I/O Pin Function
0
The I/O pin is in input mode. Data is written into the output data latch.
0
1
Data is written into the output data latch and output to the I/O pin.
1
0
The state of the I/O pin is read.
1
The I/O pin is in an output mode. The output data latch is read.
TPG
22
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
| MC68HC05J1A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05J1ACDW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05J1ACP | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
| MC68HC05J1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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