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參數(shù)資料
| 型號(hào)： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁(yè)數(shù)： | 101/124頁(yè) |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MOTOROLA
8-12
MC68HC05G1
SERIAL PERIPHERAL INTERFACE
8
MODF bit is normally a logic zero and is set only when the master device has its SS pin pulled
low. Toggling the MODF bit to a logic one affects the internal serial peripheral interface (SPI)
system in the following ways:
1) MODF is set and SPI interrupt is generated if SPIE=1
2) The SPE bit is forced to a logic zero. This blocks all output drive from the
device, disables the SPI system.
3) The MSTR bit is forced to a logic zero, thus forcing the device into the slave
mode.
Clearing the MODF is accomplished by a software sequence of accessing the serial peripheral
status register while MODF is set followed by a write to the serial peripheral control register.
Control bits SPE and MSTR may restored to their original set state during this clearing sequence
or after the MODF bit has been cleared. Hardware does not allow the user to set the SPE and
MSTR bit while MODF is a logic one unless it is during the proper clearing sequence. The MODF
ag bit indicates that there might have been a multi-master conict for system control and allows
a proper exit from system operation to a reset or default system state. The MODF is cleared by
reset.
8.4.3
Serial Peripheral Data I/O Register (SPDR)
The serial peripheral data I/O register is used to transmit and receive data on the serial bus.
A write to this register will initiate transmission/reception of another byte and this will only occur in
the master device. A slave device writing to this data I/O register will not initiate a transmission. At
the completion of transmitting a byte of data, the SPIF is set in both the master and slave devices.
A write or read of the serial peripheral data I/O register, after accessing the serial peripheral status
register with SPIF set, will clear SPIF.
During the clock cycle that the SPIF bit is being set, a copy of the received data byte in the shift
register is being moved to a buffer. When the user reads the serial peripheral data I/O register, the
buffer is actually being read. During an overrun condition, when the master device has sent
several bytes of data and the slave device has not internally responded to clear the rst SPIF, only
the rst byte is contained in the receive buffer of the slave device; all others are lost. The user may
read the buffer at any time. The rst SPIF must be cleared by the time a second transfer of data
from the shift register to the read buffer is initiated or an overrun condition will exist.
A write to the serial peripheral data I/O register is not buffered and places data directly into the
shift register for transmission.
The ability to access the serial peripheral data I/O register is limited when a transmission is taking
place. It is important to read the discussion dening the WCOL and SPIF status bits to understand
the limits on using the serial peripheral data I/O register.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
$2C
TPG
74
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68HC05J1 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:HCMOS MICROCONTROLLER UNIT |
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| MC68HC05J1ADW | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Microcontrollers |
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