參數(shù)資料
型號(hào)： MC68HC05G1B
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝： SDIP-56
文件頁數(shù)： 96/124頁
文件大?。?/td> 732K
代理商： MC68HC05G1B
MC68HC05G1
MOTOROLA
8-7
SERIAL PERIPHERAL INTERFACE
8
8.4.1.1
SPIE - Serial Peripheral Interrupt Enable
1 (set)
–
Serial Peripheral Interrupt Enabled
0 (clear) –
Serial Peripheral Interrupt Disabled
Figure 8-3 Serial Peripheral Interface Block Diagram
RATE
GENERATOR
INTERNAL
PROCESSOR
CLOCK
MASTER
START LOGIC
SLAVE
START LOGIC
CONTROL BITS
SCK
MOSI
MISO
READ BUFFER
8-BIT SHIFT
REGISTER
STATE
CONTROLLER
FLAGS
(LOAD)
(FULL)
WRITE
SPCR
SPSR
SS
2
3
7
8
READ
INTERNAL
D
AT
A
B
U
S
Note:
SS, SCK, MOSI, and MISO are external pins; where
SS
-
provides a logic low to select a slave device for a transfer with a master device.
SCK
-
provides system clock when device is congured as a master unit. Receives system clock
when device is congured as a slave unit.
MOSI
-
provides serial output to slave unit(s) when device is congured as a master. Receives serial
input from master when device is congured as a slave unit.
MISO
-
receives serial input from slave unit(s) when device is congured as a master. Provides serial
output to master when device is congured as a slave unit.
TPG
69
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