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參數(shù)資料
| 型號： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 94/124頁 |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
8-5
SERIAL PERIPHERAL INTERFACE
8
8.2.3
Slave Select (SS)
The slave select (SS) pin is a xed input which receives an active low signal that is generated by
the master device to enable slave device(s) to accept data. To ensure that data will be accepted
by a slave device, the SS signal line must be a logic low prior to occurrence of serial SCK and must
remain low until after the last (eighth) SCK cycle. Figure 8-2 illustrates the relationship between
SCK and the data for two different level combinations of CPHA, when SS is pulled low. These are:
1) with CPHA = 1 or 0, the rst bit or data is applied to the MISO line for transfer, and 2) when
CPHA = 0 the slave device is prevented from writing to its data register. Refer to the WCOL status
ag in the serial peripheral status register (bit 6, location $2B) description for further information
on the effects that the SS input and CPHA control bit have on the I/O register. A high level SS
signal forces the MISO line to the impedance state. Also, SCK and the MOSI line are ignored by
a slave device when its SS signal is high.
When the device is a master, it constantly monitors its SS signal input for a logic low. the master
device will become a slave device any time its SS signal is detected low. This ensures that there
is only one master controlling the SS line for a particular system. When the SS line is detected
low, it clears the MSTR control bit in the SPSR (bit 4, location $2A). Also, control bit SPE in the
SPCR (bit 6, location $2A) is cleared and causes the serial peripheral interface to be disabled. The
MODF ag bit in the serial peripheral status register (location $2B) is also set to indicate to the
master device that another device is attempting to become a master. Two devices attempting to
be outputs are normally the result of a software error; however, a system could be congured
which would contain a default master which would automatically “take-over” and restart the
system.
8.2.4
Serial Clock (SCK)
The serial clock is used to synchronize the movement of data both in and out the device through
its MOSI and MISO pins. The master and slave devices are capable of exchanging a data byte of
information during a sequence of eight clock pulses. Since SCK is generated by the master
device, the SCK line becomes an input in all slave devices and synchronizes slave data transfer.
The type of clock and its relationship to data are controlled by the CPOL and CPHA bits in the
SPCR (location $2A). Refer to Figure 8-2 for timing.
The master device generates the SCK through a circuit driven by the internal processor clock. Two
bits (SPR0 and SPR1) in the SPCR (location $2A) of the master device select the clock rate. The
master device uses the SCK to latch incoming slave device data on the MISO line and shifts out
data to the slave device on the MOSI line. Both master and slave devices must be operated in the
same timing mode as controlled by the CPOL and CPHA bit in the SPCR. In the slave device,
SPR0, SPR1 have no effect on the operation of the serial peripheral interface. Timing is shown in
TPG
67
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