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參數(shù)資料
| 型號： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 80/124頁 |
| 文件大?。?/td> | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
7-5
PROGRAMMABLE TIMER
7
contains the free-running counter value that corresponds to the most recent input capture.After a
read of the input capture register MSB ($14), the counter transfer is inhibited until the LSB ($15)
is also read. This characteristic causes the time used in the input capture software routine and its
interaction with the main program to determine the minimum pulse period. A read of the input
capture register LSB ($15) does not inhibit the free-running counter transfer since they occur on
opposite edges of the internal bus clock.
7.4
Timer Control Register (TCR)
The TCR is a read/write register containing ve control bits. Three bits control interrupts
associated with each of the three ag bits found in the timer status register (discussed below). The
other two bits control: 1) which edge is signicant to the input capture edge detector (i.e., negative
or positive), and 2) the next value to be clocked to the output level registers in response to a
successful output compare. The timer control register and the free-running counter are the only
sections of the timer affected by reset. The TCMP pin is forced low during external reset and stays
low until a valid compare changes them to high. Denition of each bit is as follows:
ICIE - Input Capture Interrupt Enable
1 (set)
–
Input Capture interrupt enabled.
0 (clear) –
Input Capture interrupt disabled.
OCIE - Output Compare Interrupt Enable
1 (set)
–
Output Compare interrupt enabled.
0 (clear) –
Output Compare interrupt disabled.
TOIE - Timer Overow Interrupt Enable
1 (set)
–
Timer Overow interrupt enabled.
0 (clear) –
Timer Overow interrupt disabled.
IEDG - Input Edge
1 (set)
–
TCAP is positive-going edge sensitive.
0 (clear) –
TCAP is negative-going edge sensitive.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on Reset
$12
ICIE
OCIE
TOIE
IEDG
OLVL
000- --u0
TPG
55
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