參數(shù)資料
型號: MC68HC05G1B
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
封裝: SDIP-56
文件頁數(shù): 68/124頁
文件大?。?/td> 732K
代理商: MC68HC05G1B
MOTOROLA
6-2
MC68HC05G1
CLOCKS
6
STPOSC - Stop Oscillator
1 (set)
Oscillator is disabled in Stop mode
0 (clear) –
Oscillator is enabled in Stop mode
PLLI
1 (set)
PLL clock is stable
0 (clear) –
PLL clock is not yet stable
CLKS is the bit to select CPU clock either coming from the phase lock loop or from the 32KHz
clock. During power-up or external reset, this bit is cleared to indicate that CPU clock is from the
32KHz clock. Setting the STPOSC bit will disable the oscillator in Stop mode. The following is an
example of how to use the PLL to obtain an accurate CPU clock.
BSET
7,$24
Select PLL clock for CPU.
BSET
5,$24
Select 1.302 MHz as internal bus frequency.
JSR
DELAY
Wait a moment due to finite delay of PLLI bit
BRCLR
0,$24,*
Wait until PLL clock is stable.
JMP
SERVE
Clock is now stable, go to perform jobs that
require accurate frequency (such as Timer).
The PLL consists of an on-chip VCO, a phase comparator and a programmable divide-by-N
counter. A lter is required to lter the phase comparator output to provide a DC signal to control
the VCO frequency; see Figure 6-1.
The phase comparator compares the rising edge of an 1KHz reference signal derived from the
32KHz crystal clock to the rising edge of the VCO clock after being divided by the divide-by-N
counter. When there is phase different between the two signals, the phase comparator output will
adjust the DC level input to the VCO to change the VCO frequency; see Figure 6-2. The
divide-by-N counter can be programmed to divide by different rates to obtain 4 different VCO
frequencies of 288KHz, 576KHz, 2.604MHz, and 5.208MHz. Refer to Figure 12-3 and
Figure 12-4 for external low-pass lter components.
Figure 6-1 Phase Lock Loop Block Diagram
External
Low-Pass
Filter
OSC
PHASE
DETECTOR
VCO
÷ N
PLL CLOCK FOR CPU
32.768KHz
VCOIN
PCOUT
OSC1
OSC2
1KHz
TPG
44
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