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參數(shù)資料
| 型號： | MC68HC05G1B |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56 |
| 封裝： | SDIP-56 |
| 文件頁數(shù)： | 100/124頁 |
| 文件大小： | 732K |
| 代理商： | MC68HC05G1B |
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MC68HC05G1
MOTOROLA
8-11
SERIAL PERIPHERAL INTERFACE
8
the same sequence. If a second transfer has started while trying to clear (the previously set) SPIF
and WCOL bits with a clearing sequence containing a write to the serial peripheral data register,
only the SPIF bit will be cleared.
A collision of a write to the serial peripheral data register while an external data transfer is taking
place can occur in both the master mode and the slave mode, although with proper programming
the master device should have sufcient information to prevent this collision.
Collision in the master device is dened as a write of the serial peripheral data register while the
internal rate clock (SCK) is in the process of transfer. The signal in the SS pin in always high on
the master device.
A collision in a slave device is dened in two separate modes. One problem arises in a slave
device when the CPHA control bit is a logic zero. When CPHA is a logic zero, data is latched with
the occurrence of the rst clock transition. The slave device does not have any way of knowing
when that transition will occur; therefore, the slave device collision occurs when it attempt to write
the serial peripheral data register after its SS pin has been pulled low. The SS pin of the slave
device freezes the data in its serial peripheral data register and does not allow it to be altered if
the CPHA bit is logic zero. The master device must raise the SS pin of the slave device high
between each byte it transfer to the slave device.
The second collision mode is dened for the state of the CPHA control bit being a logic one. With
the CPHA bit set, the slave device will be receiving a clock (SCK) edge prior to the latch of the rst
data transfer. This rst clock edge will freeze the data in the slave device I/O register and allow the
most signicant bit onto the external MISO pin of the slave device. The SS pin low state enables
the slave device but the drive onto the MOSI pin does not take place until the rst data transfer
clock edge. The WCOL bit will only be set if the I/O register is accessed while a transfer is taking
place. By denition of the second collision mode, a master device might hold a slave device SS
pin low during a transfer of several bytes of data without a problem.
A special case of write collision occurs in the slave device. This happens when the master device
starts a transfer sequence (an edge of SCK for CPHA=1; or an active SS transition for CPHA=0)
at the same time the slave device CPU is writing to its serial peripheral interface data register. In
this case it is assumed that the data byte written (in the slave device serial peripheral interface) is
lost and the contents of the slave device read buffer becomes the byte that is transferred. Because
the master device receives back the last byte transmitted, the master device can detect that a fatal
write collision occurred.
Since the slave device is operating asynchronously with the master device, the WCOL bit may be
used as an indicator of a collision occurrence. This helps to alleviate the user from a strict real-time
programming effort. The WCOL bit is cleared by reset.
8.4.2.3
MODF - Mode Fault
The function of the mode fault ag bit is dened for the master mode (device). If the device is a
slave device the MODF bit will be prevented from toggling from a logic zero to a logic one;
however, this does not prevent the device from being in the slave mode with MODF bit set. The
TPG
73
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