2.11 Watchdog Timer, Timebase Timer Functions
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(2) Timebase Timer
The timebase timer functions as clock source for the watchdog counter, a timer for main clock and PLL
clock oscillation stabilization time, and as an interval timer generating interrupts at regular designated
intervals.
s Timebase Timer
The timebase timer consists of an 18-bit counter that counts the oscillator input to produce the machine
clock. The count operation is continuous as long as the oscillator signal is input. The timebase timer is
cleared by a power-on reset, by transition to stop mode or hardware standby mode, by transition from
main clock to PLL clock by setting the MCS bit in the CKSCR register, or by writing ‘0’ to the TBR bit
in the TBTC register.
Clearing the timebase timer affects the watchdog counter and interval interrupt functions that operate
using the output from the timebase timer.
s Interval Interrupt Function
This function generates interrupts at regular intervals according to the timebase counter carry signal.
The TBOF flag is set after each occurrence of an interval determined by the TBC1, TBC0 bits in the
TBTC register. The setting of this flag is based on the last time that the timebase timer was cleared.
In a transition from main clock mode to PLL clock mode, the timebase timer is cleared because it is
used as the timer for PLL clock oscillation stabilization wait time.
In transition to stop mode or hardware standby mode, the time base timer is used to time the oscillation
stabilization period after recovery. Therefore the TBOF flag is cleared simultaneously with mode
transition.