2.4 Multi-Function Timer
86
Chapter 2: Hardware
(10) Compare Clear Buffer Register and Compare Clear Register (CLRBR, CLRR)
This register and buffer register store compare values used for the compare-clear function.
When the value in this register matches the timer value, the timer is cleared or switches to down-count
operation.
While the timer is operating, data is transferred from the buffer register to the compare clear register
when the timer value is 0000H. This transfer is controled by the TREN bit in the CMCR register.
Also, when using the zero-detect interrupt mask function, the TMSK bit in the CMCR register can be
used to determine whether data will be transferred from buffer registers to compare registers while the
zero-detect interrupt is masked.
Note:
Access by read-modify type instructions may cause abnormal operation and should not be
attempted with these registers.
When a match is detected between the value in this register and the timer value, the timer will be
cleared if the MODE bit in the TMCR register is ‘0.’ If the MODE bit is ‘1,’ the timer will switch from
up-count to down-count operation.
If the match occurs simultaneously with an OCPR register match, the MB90660A series chip will
simultaneously execute both the pin control according to the OCPR register match, and the timer clear
function according to the compare-clear match.
If the match occurs simultaneously with an OCPR register match in up/down mode, pin controls will
operate during down-counting.
If the value in this register is 0000H, no CLRR register match detect operations will be executed.
–
CL13 CL12 CL11 CL10 CL09 CL08
Initial value
W
CLRR
15
14
13
12
11
10
9
8
--000000B
W
bit
–
CL13 CL12 CL11 CL10 CL09 CL08
--000000B
CLRBR
Address : 000051H
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
Initial value
W
CLRR
7
6
5
4
3
2
1
0
00000000B
W
bit
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
00000000B
CLRBR
Address : 000050H