3.3 Interrupts
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Chapter 3:Operation
3.3 Interrupts
The F2MC-16L has an interrupt function that interrupts the current processing when a predefined event,
etc., occurs, and shifts control to a separately defined program. Interrupt functions can be divided into the
following four types:
Hardware interrupts: ....................................... Interrupt processing caused by the occurrence of an
event in an on-chip resource
Software interrupts: ........................................ Interrupt processing caused by an instruction
generating a software event
Extended Intelligent I/O Service (EI2OS): ..... Transfer processing caused by the occurrence of an
event in an on-chip resource
Exceptions: ..................................................... An interruption of processing caused by the
occurrence of an operating exception
This section explains these four interrupt functions.
3.3.1 Hardware Interrupts
(1) Overview
The hardware interrupt function temporarily interrupts program execution by the CPU in response to an
interrupt request signal from an on-chip peripheral resource and shifts control to a user-defined
interrupt processing program. The hardware interrupt is started up by comparing the interrupt level of
the interrupt request with the interrupt level mask register in the CPU’s PS register and then referencing
via the hardware the contents of the I flag in the PS; then, if the conditions for generating the interrupt
are met, the interrupt is generated. The processing performed by the CPU when a hardware interrupt is
generated includes the following:
Saving the contents of the PC, PS, AH, AL, PCB, DTB, ADB, and DPR registers within the CPU
into the system stack
Setting the ILM bits in the PS register automatically to the same level as that of the interrupt
currently being requested
Fetching the contents of the corresponding interrupt vector and then branching there
(2) Structure
The facilities related to hardware interrupts can be grouped into three parts:
On-chip resources: ..... Interrupt enable bit and interrupt request bit (Control of interrupt
requests from resources)
Interrupt controller: .... ICR (Interrupt level assignment and determination of priority of
simultaneously requested interrupts)
CPU: ........................... I, ILM (Comparison of level of requested interrupt with current level,
identification of interrupt enable state)
Microcode (Interrupt processing steps)
The on-chip resources are represented through the contents of the resource control register. The
interrupt controller is represented through the contents of the ICR. The CPU is represented through the
contents of the CCR, etc. When using hardware interrupts, these three settings must be made
beforehand through software.
The interrupt vector table referenced during interrupt processing is assigned to the memory area from
FFFC00H to FFFFFFH; this table is also used by software interrupts. The assignments in this device are
shown in Table 3.3.1.