2.9 External Interrupts
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2.9.3 Detailed Register Descriptions
(1) ENIR (Interrupt Enable Register)
s Register Configuration
s Register Description
The ENIR register is used to have the device pin serve as an external interrupt request input and to
determine the operation of the external interrupt request input functions that generate interrupt requests
to the interrupt controller. When ‘1’ is written to a bit in this register, the corresponding pin is used as
an external interrupt request input and has the function of generating interrupt requests to the interrupt
controller. When ‘0’ is written to a bit, the corresponding pins will store external interrupt request input
source, but will not generate requests to the interrupt controller.
(2) EIRR (Interrupt Source Register)
s Register Configuration
s Register Description
The EIRR register can be read-accessed to show the presence of external interrupt requests, and can be
write-accessed to clear the flip-flop settings that indicate these requests. A read value of ‘1’ indicates
that an external interrupt request has been made at the pin corresponding to that bit. Writing ‘0’ to this
register clears the request flip-flop setting at the corresponding bit. Writing ‘1’ has no effect in
operation. For read-modify-write instructions, the read value is always ‘1.’
[CAUTION]
In interrupt-enabled status, write-access to this register should write '0' only to bit(s) that
have been set to ‘1.’ This is to avoid unconditional clearing of other flag bits that are not
the flag bits for sources that have been set by interrupt requests.
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
Bit no.
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(0)
Interrupt enable register
Address : 000028H
7
6
5
4
3
2
1
0
ENIR
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Bit no.
Read/write
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
Initial value
(X)
Interrupt source register
Address : 000029H
15
14
13
12
11
10
9
8
EIRR