
3.5 Low Power Consumption Modes
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Chapter 3:Operation
3.5 Low Power Consumption Modes
The MB90660A supports the following operating modes: PLL clock mode, PLL sleep mode, watch mode,
main clock mode, main sleep mode and stop mode. All modes other than PLL clock mode are classified as
low-power consumption modes.
In main clock mode and main sleep mode, the main clock (OSC oscillator clock) signal operates alone, the
operating clock signal is produced by dividing the main clock signal by two, and the PLL clock (VCO
oscillator clock) signal is stopped. In PLL sleep mode and main sleep mode, only the CPU operating clock
is stopped, and all other clock signals operate. In watch mode, only the timebase timer operates. Stop
mode, in which all oscillators are stopped, is the lowest power-consumption mode in which data values are
retained.
The CPU intermittent operation function allows the clock signal feed to the CPU to operate intermittently
for registers, internal memory, internal resources or external bus access. This enables reduced power
consumption by lowering the CPU execution speed while maintaining the high speed clock feed to internal
resources.
The PLL clock multiplier rate is set using the CS1, CS0 bits and may be selected from either 1, 2, 3, or 4
times the clock signal feed.
Table 3.5.1 shows the MB90660A chip operating status in each of its operating modes.
Table 3.5.1 Low-power Consumption Modes and Operating State
Transition
conditions
Oscillator
Clock
CPU
Peripheral
resources
Pins
Mode
exited by
Main sleep
mode
MCS=1
SLP=1
Operation
Stopped
Operation
Reset or
interrupt
PLL sleep
mode
MCS=0
SLP=1
Operation
Stopped
Operation
Reset or
interrupt
Watch mode
(SPL=0)
MCS=0
STP=1
Operation
Stopped
Retain pre-
vious status
Reset or
interrupt
Watch mode
(SPL=1)
MCS=0
STP=1
Operation
Stopped
HI-Z
Reset or
interrupt
Stop mode
(SPL=0)
MCS=1
STP=1
Stopped
Retain pre-
vious status
Reset or
interrupt
Stop mode
(SPL=1)
MCS=1
STP=1
Stopped
HI-Z
Reset or
interrupt