2.7 PWM
151
(2) Reload Values and Pulse Widths
‘The value written to the reload register plus one (+1)’ is multiplied by the period of the count clock and
the result is the width of the output pulse. Note that this means, if the reload register has a value of 00H,
the pulse width will be equal to one period of the count clock. The following formulas determine the
calculation of the pulse width.
L: PRLL value
Pl = T × (L+1) s
H: PRLH value
Ph = T × (H+1) s
T: count clock
Ph: high-level pulse width
Pl: low-level pulse width
(3) Count Clock Selection
The count clock used for PWM operations uses the output signal of a peripheral clock unit. There is a
selection of two types of count clock input.
When bit 6 (PCKS) in the PWMC register is ‘0’ the count clock will be the main clock signal divided
by 29.
When bit 6 (PCKS) in the PWMC register is ‘1’ the count clock will be the main clock signal divided
by 22.
Note that irregularity may occur in the first count clock period after the PWM is started by a trigger
signal, or the first period after the unit stops.
(4) Pulse Pin Output Control
Pulse output signals produced by the PWM module can be output from the external PWM pins.
The external pin output is enabled by bit 5 (POE) in the PWMC register. When this bit is ‘0’ (its initial
value), no pulse signal is output from the external pins, and the pins function as a general-purpose port.
When this bit is set to ‘1’ the PWM pulse signal is output from the external pins.
(5) Reload Register Write Timing
Writing to the reload registers PRLL and PRLH should be performed using word transfer instructions.
Unintended pulse widths may result from writing using two repeated byte transfer instructions in some
timings.
On the above timing chart the PRLL value is rewritten from A to C before point (1), and the PRLH
value is rewritten from B to D after point (1). Thus at timing (1) the PRL values are PRLL=C, PRLH=B
so that for only one pulse cycle the L-level has a count value of C and the H-level has a count value of
B.
PWM
B
C
A
D
A
D
B
C
B
(1)