
1.6 Pin Description
8
Chapter 1: Overview
61
5
P42
E (CMOS/H)
General-purpose I/O port. This function is enabled
when UART clock output is disabled.
SCK
UART clock I/O pin. This function is enabled when
UART clock output is enabled. When UART input oper-
ation is in progress, this pin remains set for input func-
tions at all times, therefore output from all other
functions must be disabled unless intentionally exe-
cuted.
62
6
P43
E (CMOS/H)
General-purpose I/O port. This function is enabled
when the PWM output is disabled.
PWM
PWM timer output pin. This function is enabled when
the PWM timer waveform output is enabled.
63
64
7 to 8
P44 to P45
D (CMOS/H)
General-purpose input ports. This function is enabled at
all times.
INT0 to INT1
External interrupt request pins. When external interrupt
functions are enabled, these pins remain set for input
functions at all times.
1
9
P46
D (CMOS)
General-purpose input port. This function is enabled at
all times.
INT2
External interrupt request pin. When external interrupt
functions are enabled, these pins remain set for input
functions at all times.
TRG
Multi-function timer ‘timer clear’ trigger input pin. This
input function is used at all times when multi-function
timer input is enabled.
2
10
P47
D (CMOS/H)
General-purpose input port. This function is enabled at
all times.
INT3
External interrupt request pin. When external interrupt
functions are enabled, these pins remain set for input
functions at all times.
ATGX
A/D converter trigger input pin. This input function is
used at all times when A/D converter input is operating.
3 to 10
11 to 18
P50 to P57
C (AD)
Open-drain type I/O ports. This function is enabled
when the analog input enable register is set for port
operation.
AN0 to AN7
A/D converter analog input pins. This function is
enabled when the analog input enable register is set for
A/D operation.
Table 1.6.1 MB90660A Pin Description (2)
Pin No.
Pin Name
Circuit Type
Function
QFP
SH-DIP