2.1 CPU
29
s Program Counter (PC)
The PC register is a 16-bit counter, indicating the lower 16 bits of the memory address containing the
instruction code to be executed by the CPU. The upper 8 bits of the address are indicated by the PCB
register. The value in the PC register is updated by branching instructions, subroutine call instructions,
interrupts and resets.
This register can also be used as a base pointer for operand access.
Fig. 2.1.16 Program Counter
s Direct Page Register (DPR) <Initial value: 01H>
The DPR register indicates the values addr8 through addr15 of the operand in direct addressing
instructions, as shown in Figure 2.1.17. The DPR register has 8-bit length, and is initialized to ‘01H’ at
a reset. Both read and write access are enabled using instructions.
Fig. 2.1.17 Generation of Physical Addresses by Direct Addressing
s Program Counter Bank Register (PCB)
<Initial value: value in reset vector>
Data Bank Register (DTB)
<Initial value: 00H>
User Stack Bank Register (USB)
<Initial value: 00H>
System Stack Bank Register (SSB)
<Initial value: 00H>
Additional Data Bank Register (ADB)
<Initial value: 00H>
This set of bank registers is used to indicate the memory banks where PC space, DT space, SP space
(user), SP space (system) and AD space are allocated respectively. All have 8-bit length. Following a
reset the PCB register is initialized to ‘FFH’ and all others to ‘00H.’ All except the PCB register are read/
write enabled. The PCB register is enabled for read access only. The PCB register is overwritten by
processing of instructions branching to full 16-Mbyte space including JMPP, CALLP, RETP and RETI,
as well as by software interrupt instructions, hardware interrupts and exception processing. The
operation of each of these registers is described in section 2.1.1 “Memory Space.”
Next instruction
to be executed
PCB
FEH
PC
ABCDH
FEABCDH
DTB register
DDR register
Direct address in instruction
24-bit
αααααααα
ββββββββ
γγγγγγγγ
ααααααααββββββββγγγγγγγγ
MSB
LSB
physical address