2.4 Multi-Function Timer
77
(2) Compare Interrupt Control Register (CICR)
This register controls interrupts due to matches between OCPR register and timer value, for each
channel separately. Interrupt requests sent to the CPU are OR-linked results of interrupt requests on the
four channels.
[Bits 15 to 12] CIE3 to CIE0: Compare-match interrupt request enable bits
CIE3: Interrupt request enable bit for CIR3
CIE2: Interrupt request enable bit for CIR2
CIE1: Interrupt request enable bit for CIR1
CIE0: Interrupt request enable bit for CIR0
[Bits 11 to 8] CIR3 to CIR0: Compare-match interrupt request flag
These bits are set to ‘1’ when a match is detected between the corresponding OCPR register value
and timer value.
To clear these bits, write ‘0’ or clear by EI2OS.
Writing ‘1’ to these bits has no effect, and will not change the bit value.
For read-modify-write instructions, the read value is always ‘1.’
Each of the four bits corresponds to an OCPR register as follows.
CIR3: set to ‘1’ when a match is detected between the value of output compare register 3
(OCPR3) and the timer value.
CIR2: set to ‘1’ when a match is detected between the value of output compare register 2
(OCPR2) and the timer value.
CIR1: set to ‘1’ when a match is detected between the value of output compare register 1
(OCPR1) and the timer value.
CIR0: set to ‘1’ when a match is detected between the value of output compare register 0
(OCPR0) and the timer value.
CIEx
Description
0
Disable compare-match interrupt request
1
Enable compare-match interrupt request
CIRx
Flag setting
0
No compare-match interrupt request
1
Compare-match interrupt request
CIE3 CIE2 CIE1 CIE0 CIR3 CIR2 CIR1 CIR0
Initial value
R/W
R/W R/W
R/W
CICR
15
14
13
12
11
10
9
8
00000000B
Address : 000041H
R/W
bit