
2.8 16-Bit Reload Timer (with Event Count Function)
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[Bit 5] OUTL
This bit sets the output level of the TOT pins. Pin levels are reversed by switching between settings
of ‘0’ and ‘1.’
Table 2.8.4 RELD, OUTL Pin Settings
[Bit 4] RELD (Reload)
This is the reload enable bit. When the value is ‘1,’ the timer is in reload mode, and each time the
counter value reaches an underflow condition from 0000H to FFFFH the contents of the reload
register are loaded into the counter and the count operation continues. The value ‘0’ takes the
single-shot operation mode and the count operation stops when the counter value reaches an
underflow condition from 0000H to FFFFH.
[Bit 3] INTE (Interrupt enable)
This is the interrupt request enable bit. When the value is ‘1’ an interrupt request is generated each
time the UF bit is set to ‘1.’ When the value is ‘0’ no interrupt request is generated even when the
UF bit is set to ‘1.’
[Bit 2] UF (Underflow)
This is the timer interrupt request bit, and is set to ‘1’ each time the counter value reaches an
underflow condition by going from 0000H to FFFFH. This bit can be cleared by writing ‘0’ or by the
intelligent I/O service. Writing ‘1’ to this bit has no effect. With read-modify-write instructions, the
read value is always ‘1.’
[Bit 1] CNTE (Count enable)
This is the timer count enable bit. Writing ‘1’ to this bit places the counter in trigger standby mode.
Writing ‘0’ to this bit stops the counting operation.
[Bit 0] TRG (Trigger)
This is the software trigger bit. Writing ‘1’ to this bit applies a software trigger, causing the contents
of the reload register to be loaded into the counter, thereby starting counter operation. Writing ‘0’ to
this bit has no effect. The read value is always ‘0.’ Trigger input from this register is valid only
when the CNTE bit is set to ‘1.’ When the CNTE bit is ‘0’ this bit has no effect.
RELD
OUTL
Output waveform
0
‘H’ square wave during count
0
1
‘L’ square wave during count
1
0
‘L’ toggle output at start of count
1
‘H’ toggle output at start of count