2.4 Multi-Function Timer
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Chapter 2: Hardware
2.4.4 Detailed Register Descriptions
(1) Timer Control Status Register (TCSR)
This register controls software timer clear, clear interrupt from triggered input, zero detect interrupt,
and overflow/compare-clear-match interrupt processing.
[Bit 7] STCR: Software timer clear bit
This bit initializes the timer.
Writing ‘0’ to this bit initializes the timer and the internal prescaler.
Writing ‘1’ to this bit is ignored and has no effect.
The read value is always ‘1.’
[Bit 6] IIOS: EI2OS interrupt function extension bit
This bit extends the interrupt functions for timer zero detection events.
Writing ‘1’ to this bit causes the TCIR bit and TMIR bit to have the same functions as the TZIR bit.
Thus when a zero-detect event occurs, not only the TZIR but also the TCIR and TMIR bits will be
simultaneously set to ‘1’ with the result that zero detection can start EI2OS on 3 channels of the
OCPBR register.
This bit should only be overwritten when the timer is stopped. Also, if this bit is overwritten, the
TCIR, TZIR and TMIR sources should be cleared before the respective interrupts are enabled.
[Bit 5] TCIE: Timer clear interrupt enable bit
This bit enables the timer clear interrupt request from an external trigger (TRG pin) input signal.
STCR
Operation
0
Clear timer and prescaler
1
No operation
IIOS
Description
0
Zero detection sets only the TZIR bit to ‘1’
1
Zero detection sets TZIR, TCIR and TMIR bits to ‘1’
TCIE
Description
0
Disable timer clear interrupt request from external trigger input
1
Enable timer clear interrupt request from external trigger input
STCR IIOS TCIE TCIR TZIE TZIR TMIE TMIR
Initial value
R/W
TCSR
7
6
5
4
3
2
1
0
10000000B
Address : 000040H
W
R/W
bit