2.10 Delayed Interrupt Generator Module
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Chapter 2: Hardware
2.10.4 Operating Description
(1) Delayed Interrupts
When the CPU uses software instructions to write ‘1’ to the DIRR register, the request latch is set in the
delayed interrupt generator module, and an interrupt request is sent to the interrupt controller. If other
interrupt requests have a lower priority, or if there are no other requests, an interrupt is then generated
to the F2MC-16L CPU, which compares the request with the ILM bit in its own internal CCR register.
If the request level is higher than the ILM bit, then as soon as the current instruction finishes executing,
the hardware interrupt processing microprogram is started. This causes the interrupt processing routine
for this interrupt to be executed.
Fig. 2.10.2 Delayed Interrupt Generator
Generator Operation during the processing routine, the interrupt source is cleared by writing ‘0’ to the
corresponding bit in the DIRR register, thereby switching tasks as well.
2.10.5 Precautionary Information
(1) Delayed Interrupt Request Latch
This latch is set by writing ‘1’ to the corresponding bit in the DIRR register, and cleared by writing ‘0’
to the same bit. Thus the interrupt processing routine must contain software to clear the source, or else
recovery from interrupt processing will only result in the start of another interrupt processing routine.
Users should ensure that interrupt processing software is structured to avoid this problem.
Delayed interrupt generator module
Other requests
Interrupt controller
F2MC-16L CPU
DIRR
ICR yy
ICR xx
CMP
IL
ILM
CMP
INTA
WRITE