2.4 Multi-Function Timer
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[bit 4] TCIR: Timer clear interrupt request flag
This flag indicates an interrupt request at the time the timer is cleared as a result of an external
trigger (TRG pin) signal input.
The flag is set to ‘1’ when the timer is cleared as a result of an external trigger (TRG pin) signal
input.
When the IIOS bit is ‘1’ this flag is set to ‘1’ when a zero-detect event occurs. Once this setting is
made, the flag cannot be set to ‘1’ by clearing the timer.
To clear this bit, write '0' or clear by EI2OS.
Writing ‘1’ to this bit is ignored and will not change the bit value.
For read-modify-write instructions, the read value is always ‘1.’
[Bit 3] TZIE: Zero detect interrupt enable bit
This bit enables an interrupt request to be generated by a zero-detect event.
[Bit 2] TZIR: Zero detect interrupt request flag
This flag indicates a timer zero-detect interrupt request.
This bit is set to ‘1’ when a timer zero-detect event occurs.
To clear this bit, write ‘0’ or clear by EI2OS.
Writing ‘1’ to this bit has no effect, and will not change the bit value.
For read-modify-write instructions, the read value is always ‘1.’
[Bit 1] TMIE: Timer interrupt request enable bit
This bit enables the timer overflow interrupt request, and the CLRR register match detect interrupt
request.
TCIR
Flag setting
0
No timer clear interrupt request from external trigger signal input
1
Timer clear interrupt request from external trigger signal input
TZIE
Description
0
Zero detect interrupt request disabled
1
Zero detect interrupt request enabled
TZIR
Flag setting
0
No zero detect interrupt request
1
Zero detect interrupt request
TMIE
Description
0
Disable overflow/compare-clear-match detect interrupt request
1
Enable overflow/compare-clear-match detect interrupt request