3.3 Interrupts
213
q Extended Intelligent I/O Service Descriptor (ISD)
The extended intelligent I/O service Descriptor (ISD) resides in internal RAM between 000100H and
00017FH, and consists of the following information:
Control data for the data transfer
Status data
Buffer address pointer
Fig. 3.3.7 shows the Extended Intelligent I/O Service Descriptor configuration.
Fig. 3.3.7 Extended Intelligent I/O Service Descriptor Configuration
s Data counter (DCT)
This 16-bit register is a counter that handles the transfer data count. Before a data transfer, the counter
is decremented by 1. Once the counter reaches zero, EI2OS terminates. Fig. 3.3.8 shows the data
counter configuration.
Fig. 3.3.8 Data Counter Configuration
s I/O Register Address Pointer (IOA)
This 16-bit register indicates the low-order addresses (A15 to A0) of the I/O register used for buffering
and data transfer. The high-order addresses are all zeroes; I/O can be specified for any address from
000000H to 00FFFFH. Fig. 3.3.9 shows the configuration of the IOA register.
Fig. 3.3.9 I/O Register Address Pointer Configuration
000100H + 8 × ICS
Data counter - highest 8 bits (DCTH)
Data counter - lowest 8 bits (DCTL)
I/O address pointer - highest 8 bits (IOAH)
I/O address pointer - lowest 8 bits (IOAL)
I2OS status (ISCS)
Buffer address pointer - highest 8 bits (BAPH)
Buffer address pointer - middle 8 bits (BAPM)
Buffer address pointer - lowest 8 bits (BAPL)
H
L
ISD top address
(Indeterminate at reset)
15
B15
14
B14
13
B13
12
B12
11
B11
10
B10
9
B09
8
B08
7
B07
6
B06
5
B05
4
B04
3
B03
2
B02
1
B01
0
B00
: DCT
(Indeterminate at reset)
15
A15
14
A14
13
A13
12
A12
11
A11
10
A10
9
A09
8
A08
7
A07
6
A06
5
A05
4
A04
3
A03
2
A02
1
A01
0
A00
: IOA