2.8 16-Bit Reload Timer (with Event Count Function)
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Chapter 2: Hardware
(6) Intelligent I/O Service (I2OS) Function and Interrupts
This timer circuit has a circuit adapted for I2OS. This means that a timer overflow can be used to start
the I2OS operation. The MB90660A has four timers, and all can be used with I2OS. Note however that
each of the interrupt control registers (ICRx) in the interrupt controller is connected to two timers (Ch0
+ Ch1, or Ch2 + Ch3), so that it is not possible to allocate different I2OS functions to Ch0 and Ch1, or
to Ch2 and Ch3 at the same time. Also, each of the four timers has its own separate interrupt vector so
that interrupts can be used for four functions simultaneously but because Ch0 and Ch1 (or Ch2 and
Ch3) share a common interrupt control register as mentioned above, each pair of channels must have
the same interrupt level.
(7) Counter Operating Status
Counter status is determined by the CNTE bit in the control register and the internal WAIT signal.
Available settings include CNTE=0, WAIT=1 (STOP status), CNTE=1, WAIT=1 (trigger WAIT
status) and CNTE=1, WAIT=0 (RUN status). Figure 2.8.9 shows the transitions among these three
status.
Fig. 2.8.9 Counter Status Transition
Trigger from TIN
: Status transition by hardware
: Status transition by register access
End load operation
Load contents of reload register
LOAD
CNTE=1,WAIT=0
into counter
TIN: Trigger input only enabled
TOT: Output initial value
Counter: Hold value at stop,
undefined immediately after
reset, until loaded
WAIT
CNTE=1,WAIT=1
TIN: Functions as TIN
TOT: Functions as TOT
Counter: Run
RUN
CNTE=1,WAIT=0
TIN: Input disabled
TOT: Output fixed
Counter: Hold value at stop,
undefined immediately after reset
STOP
CNTE=0,WAIT=1
Reset
CNTE=‘0’
CNTE=‘1’
TRG=‘0’
TRG=‘1’
RELD
UF
RELD
UF