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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 8/46頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
16
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
Database Format” on page 16. Once the internal FIFO is emptied,
the processor will signal the ProcessorComp interrupt. After
clearing the interrupt, the processor writes the next four words of
the frame, and the cycle is repeated until the entire frame has been
written. At the end of the frame, the last group of four or fewer
words is written into the memory. Instead of FrB_Write_GO, the
processor writes to location End_of_Frame, which signals the
processor to empty the FIFO, even though it may contain fewer
than four words. The processor will signal a final ProcessorComp
interrupt, at which point it is ready to begin accepting another
frame from the processor.
Reads and writes directly to the DRAM are accomplished through
a DMA submodule of the Processor Interface. For reads, the
processor will supply a start address in DMA_StartAddress, a
length value in DMA_Length, and write the DMA_Read_GO
register. The Processor Interface will fetch the required data from
the DRAM and store it in a temporary buffer, and then assert the
DMA_Done bit of the interrupt register. By polling this register,
or through interrupt, the processor can determine whether the
data is available, when it performs repeated reads to this buffer
until the data is transferred. Writes are performed similarly, by
writing the start address, length, and data words to buffers in the
Processor Interface and then writing the DMA_Write_GO bit.
The processor may then poll or be interrupted by the interrupt
register in a manner identical to that for reads.
Asynchronous Mode
The asynchronous mode is controlled by the use of a feedback
signal from the MB86976 to confirm each read/write transaction
with the processor. The Siemens c163 uses its READY input to
confirm transactions and the Philips XA-G3 uses its WAIT input.
The MB86976 will drive these signals from its READY output.
For purposes of this discussion, each of the processorsí
acknowledge signals will be referred to as READY. All transaction
mechanisms for the asynchronous processors are otherwise
identical to those of the Intel 80c32. Although the asynchronous
processors do not suffer from the latency mismatch constraint of
the 80c32, the pseudo-DMA mode for direct accesses to the DRAM
is preserved for these processors as well.
Interrupts
The MB86976 will communicate with the processor through the
assertion of its interrupt pin, INT. All interrupt sources will be
maskable so that the processor may control the communications
behavior. The 16-bit interrupt register is readable by the processor,
and the INTerruptMASK register is both readable and writable.
These are listed under the section “Interrupt and Interrupt Mask
Register” on page 32.
At power-up, all the interrupts are masked. The processor must
write to the INTerruptMASK register to enable desired interrupts.
Every interrupt source is cleared by reading the interrupt register.
Masked interrupts are asserted in the interrupt register, but not at
the interrupt pin, allowing the processor to determine the
interrupt status by polling without being interrupted.
Processor Interface Control Register Set
The Processor Interface contains 12 registers for controlling
processor interaction with the MB86976, and for counting
statistics. These are listed under the section “Interrupt and
Interrupt Mask Register” on page 32.
DRAM Interface
The 256k x 16 page mode external DRAM is used for the Frame
Buffer (transient frame storage) in addition to the Source Address
Database. The Frame Buffer Database occupies the lower 224K (0
to (224K-1)) of the DRAM in the address space 00000h-37FFFh.
The Source Address Database occupies the upper 32K (224K to
(256K-1)) of the DRAM in the address space 38000h-3FFFFh.
The Frame Buffer
The Frame Buffer Database stores a maximum of 224 frames, each
containing no more than 1023 16-bit words, or 2046 Bytes. Bits
are stored msb to lsb.
Each table entry is comprised of a minimum of 2 and a maximum of
1023 16-bit words, as shown in table below.
Frame Buffer Database Format
bit[15:5]
bit[4:2]
bit[1:0]
length
destination
source
data value(0)
data value(1)
...
data value(n)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB86977 | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86977PFV-G-BND | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:IP PACKET FORWARDING ENGINE |
| MB86A21PMC-G-BNDE1 | 制造商:FUJITSU 功能描述: |
| MB86A21PMC-G-JNE1 | 制造商:FUJITSU 功能描述: |
| MB86A22PMC-ES-BNDE1 | 制造商:FUJITSU 功能描述: |
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