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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 45/46頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MB86976PF-G |
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xDSL WAN Ethernet Bridge Controller
8
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
Processor Interface
DRAM Interface
LED Interface
Pin Name
Pin No.
Type
Description
CPD[15:0]
15-17, 20-
29, 31-33
B(pu)
Processor Data Bus: Data transfers take place over this bus.
BYTEWORD
130
I(pu)
Processor Byte Wide/Word Wide Interface Select: =0 Selects 8-bit, =1 selects 16-bit pro-
cessor interface.
CPRD
44
I
Processor Read: Active low signal for Read operations.
CPCS
35
I
Processor Chip Select: Active low signal.
CPWR
43
I
Processor Write: Active low signal for Write operations.
CPUSEL[1:0]
129,128
I(pu)
Processor Select: Selects the type of processor that is being used.
00: Selects an Intel 80c32 or Philips XA-G3 family of microcontrollers.
01: Selects a Siemens c163 family of microcontrollers.
10-11: Reserved
CPA[8:0]
3-7,
10-13
I(pu)
Processor Address Bus: MB86976 Register Address space.
INT
40
O
Interrupt: Active low signal. Asserted by the MB86976 when it needs service by the
microcontroller. NOT open-drain, cannot be wire-ANDed.
READY
41
O
Ready: Active low signal. Acknowledge completion of bus transaction. Cannot be wire-
ANDed.
Pin Name
Pin No.
Type
Description
RAMA[8:0]
83-87, 47-
50
O
DRAM Address Bus: Multiplexed Row and Column Addresses.
RAS
51
O
Row Address Strobe: Active low signal. Addresses the row on the DRAM.
CAS
80
O
Column Address Strobe: Active low signal. Addresses the column on the DRAM.
RAMWE
52
O
Write Enable: When low, enables writes to the DRAM. When high, enables read from the
DRAM.
RAMOE
82
O
Output Enable: Enables read from the DRAM.
DQ[15:0]
64,
67-69, 71,
75, 77, 78,
56-63
B(pu)
Data Input/Output: All DRAM data transfers take place over this bus, and are 16 bit
wide. Upper and Lower Column Address Strobe lines on byte-capable memo-
ries need to be tied together.
Pin Name
Pin No.
Type
Description
LEDWR
141
O
WAN Receive Active LED: Asserted when receiving data on the WAN port.
LEDWX
143
O
WAN Transmit Active LED: Asserted when transmitting data on the WAN port.
LEDLL
140
O
Link LED: Asserted when the 10BASE-T link is operational, from LINK pin.
LEDLR
136
O
LAN Receive Active LED: Asserted when receiving on the LAN port.
LEDLX
139
O
LAN Transmit Active LED: Asserted when transmitting on the LAN port.
LEDCX
134
O
LAN Collision LED: Asserted when a collision is detected on the LAN.
LEDER
135
O
Error LED: Active for any internal buffer or FIFO overflow.
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