參數(shù)資料
型號(hào)： MB86976PF-G
元件分類(lèi)： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁(yè)數(shù)： 21/46頁(yè)
文件大?。?/td> 212K
代理商： MB86976PF-G
xDSL WAN Ethernet Bridge Controller
28
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
LAN_RxControl (LAN Receive Control Register 10)
This register affects the way in which Ethernet traffic is being received on the LAN interface. To receive an interrupt after each packet, set
the good enable and all the error enable bits, and clear bit 13, MacRxInterrupt, of the INTerruptMASK, reg 42h. Interrupts may also be
enabled only for specific conditions.
It is very strongly recommended that neither LongEn nor ShortEn be asserted (set to one), as correct operation of the MB86976 in all
cases then cannot be guaranteed.
* The frame lengths above do not include preamble and Start Frame Delimiter (SFD).
MAC_RxStatus (MAC Receive Status Register 14).
Bit
Symbol
Type
Description
0
Rx_EN
RW0
Receive Enable: If zero, stop reception immediately.
1
Rx_Halt
RW0
Receive Halt Request: Halt reception after completing any current packet.
2
Long_EN
RW0
Long Enable: Allow reception of frames longer than 1518 bytes
3
Short_EN
RW0
Short Enable: Allow reception of frames shorter than 64 bytes.
4
Strip_CRC
RW0
Strip CRC Value: Check the CRC, but strip it from the message.
5
0
N
Reserved: Unassigned.
6
Ignore_CRC
RW0
Ignore CRC Value: Do not check the CRC.
7
0
N
Reserved: Unassigned.
8
En_Align
RW0
Enable Alignment: Interrupt upon receipt of a packet whose length in bits is not a multiple of eight, and
whose CRC is invalid.
9
En_CRC_Err
RW0
Enable CRC Error: Interrupt upon receipt of a packet whose CRC is invalid.
10
En_OverFlow
RW0
Enable Overflow: Interrupt upon receipt of a packet when the MAC receive FIFO is full.
11
En_Long_Error
RW0
Enable Long Error: Interrupt upon receipt of a frame longer than 1518 bytes, unless the long enable bit is
set.
12
0
N
Reserved: Unassigned.
13
En_Rx_Par
RW0
Enable Receive Parity: Interrupt if the MAC receive FIFO has an internal parity error.
14
En_Good
RW0
Enable Good: Interrupt upon receipt of a packet with no errors.
15
0
N
Reserved: Unassigned.
Bit
Symbol
Type
Description
5:0
N
Reserved
6
IntRx
RW0
Set if reception of packet caused any interrupt condition (includes En_Good).
7
Rx10Stat
RW0
= 1 if packet was received via the 10-Mb/s interface, = 0 invalid internal mode.
8
AlignErr
RW0
Frame length in bits was not a multiple of eight and the CRC was invalid.
9
CRCErr
RW0
CRC at end of packet did not match computed value.
10
Overflow
RW0
The MAC receive FIFO was full when it needed to store a received byte.
11
LongErr
RW0
Received a frame longer than 1518 bytes.* Not set if the En_Long_Error bit in the LAN_RxControl
register, register 10, is set.
12
N
Reserved
13
RxPar
RW0
MAC receive FIFO has detected an (internal) parity error.
14
Good
R0
Successfully received a packet with no errors. If En_Good = 1 (LAN_RxControl, Reg. 10), an inter-
rupt is generated on each packet received successfully
15
RxHalted
RW0
Reception interrupted by clearing RxEn or setting RxHalt.
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