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參數(shù)資料
| 型號： | MB86976PF-G |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144 |
| 封裝： | PLASTIC, QFP-144 |
| 文件頁數(shù)： | 33/46頁 |
| 文件大?。?/td> | 212K |
| 代理商： | MB86976PF-G |
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MB86976
Fujitsu Microelectronics, Inc.
39
Advanced 11/5/98
WAN_Rx_Frames (WAN Received Frames. Register AE)
CPU_Tx_Frames (CPU Transmit Frames. Register B0)
WAN_Tx_Frames (WAN Transmit Frames. Register B2)
CPU_HiWtr_Level (CPU High Level. Register B4)
LAN_HiWtr_Level (Lan High Level. Register B6)
WAN_HiWtr_Level (WAN High Level. Register B8)
MASTER_HiWtr_Level (Master High Level. Register BA)
Note:
The “HighWaterLevel” counters indicate the worst depth of frame “pile-up” that occurred in the FrameBuffer for that type of destination port since
the last time that register was read.
DRAM_Init_Done (DRAM Initialization Done. Register BC)
Bit
Symbol
Type
Description
15:0
WAN_Rx_Frames
R0
WAN_Receive Frames: Total number of frames received on the WAN receive port.
Bit
Symbol
Type
Description
15:0
CPU_Tx_Frames
R0
CPU Transmit Frames: Total number of frames transmitted by the CPU.
Bit
Symbol
Type
Description
15:0
WAN_Tx_Frames
R0
WAN Transmit Frames : Total number of frames transmitted by the WAN.
Bit
Symbol
Type
Description
15:0
CPU_HiWtr_Level
RO
CPU High Level: Indicates the maximum number of frames in the CPU Tx FIFO.
Bit
Symbol
Type
Description
15:0
LAN_HiWtr_Level
R0
LAN High Level: Indicates the maximum number of frames in the LAN Tx FIFO.
Bit
Symbol
Type
Description
15:0
WAN_HiWtr_Level
R0
WAN High Level: Indicates the maximum number of frames in the WAN Tx FIFO..
Bit
Symbol
Type
Description
15:0
MSTR_HiWtr_Level
R0
Master High Level: Is the sum of the LAN, WAN and CPU HiWtr_Levels.
Bit
Symbol
Type
Description
0
DRAM_Init_Done
R0
DRAM Status: Asserted when the initialization of the DRAM has taken place just after power-up.
7:1
0
N
Reserved: Unassigned.
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