參數(shù)資料
型號(hào)： MB86976PF-G
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP144
封裝： PLASTIC, QFP-144
文件頁數(shù)： 17/46頁
文件大小： 212K
代理商： MB86976PF-G
xDSL WAN Ethernet Bridge Controller
24
Fujitsu Microelectronics, Inc.
Advanced 11/5/98
Internal Register Address Map
Listed by numerical address offset. Groups refer to the bit map tables that follow, and are interleaved in this map. .
System
Addr.
Offset
(Hex)
Registers
Initial
Value
Symbol
Group
Reg.
Size
(Bits)
Description
000
MAC_Control
LAN
16
MAC basic operating mode Control.
0000
004
CAM_Control
LAN
8
CAM Control, types of MAC addresses to accept.
00
008
LAN_TxControl
LAN
16
LAN Transmit option Control.
0000
00C
MAC_TxStatus
LAN
16
LAN Transmit Status, collision count, interrupt, carrier sense.
0000
010
LAN_RxControl
LAN
16
LAN Receive option Control, long/short, no CRC, interrupt...
0000
014
MAC_RxStatus
LAN
16
LAN Receive Status, long/short, CRC, alignment, etc.
0000
034
ALIGN_CNT
LAN
16
Counts LAN packets received with alignment error.
0000
038
CRC_CNT
LAN
16
Counts LAN packets received with CRC error.
0000
03C
MISS_CNT
LAN
16
Counts LAN packets received with system problem error.
0000
040
INTERRUPT
CPU
16
Read the interrupt sources.
0000
042
INTerruptMASK
CPU
16
Mask interrupt sources.
0000
048
FrameBuffer
CPU
8 or 16
Read/Write FIFOs for frames CPU <-> MB86976.
00/00
04A
End_of_Frame
CPU
1
Asserted for last transfer of sent frame.
0
04C
FrB_Write_GO
CPU
1
Transfer current send frame words to MB86976 FrameBuffer.
0
04E
FrB_Read_GO
CPU
1
Transfer current receive frame words from Frame Buffer.
0
050
DMA_StartAddress
CPU
24
Register to hold the start address of DMA transfer (18 bits).
00 0000
054
DMA_Length
CPU
4
Register to hold length, in words, of DMA transfer.
0
056
DMA_Read_GO
CPU
1
Asserted to begin DMA read operation.
0
05A
DMA_Write_GO
CPU
1
Asserted to begin DMA write operation.
0
05E
DMA_FIFO
CPU
8 or 16
Top of Data FIFO for DMA transactions.
00/00
068
HDLC_Address
WAN
8
HDLC Address Field, common to all protocols.
FF
06A
HDLC_Control
WAN
8
HDLC Control Field, common to all protocols.
03
06C
PPP_Protocol
WAN
16
First & Second byte of PPP protocol field.
4100
06E
LEX_FIZO
WAN
8
PPP-LEX FIZO Field.
00
070
LEX_MacType
WAN
8
PPP-LEX MACTYPE Field.
01
072
WAN_TxControl
WAN
8
Control register configures the WAN transmit operation.
00
074
WAN_RxControl
WAN
8
Control register to configure the WAN receive operation.
00
076
WAN_TxStatus
WAN
8
WAN Transmit Status register to report on the last result.
00
078
WAN_RxStatus
WAN
8
WAN Receive Status register to report on the last result.
00
07A
WAN_RxByte_Cnt
WAN
32
WAN Receive Byte Count, every byte received from WAN.
0000 0000
07E
WAN_RxFrame_Cnt
WAN
16
WAN Receive Frame Count, every frame received.
0000
080
WAN_RxErr_Cnt
WAN
16
WAN Receive Frame Error Count, every frame with an error.
0000
082
WAN_RxOverLength
WAN
16
Counts every frame exceeding the WAN Max, 1526 bytes.
0000
084
WAN_TxByte_Cnt
WAN
32
WAN Transmit Byte Count, every transmitted byte.
0000 0000
088
WAN_TxFrame_Cnt
WAN
16
WAN Transmit Frame Count, every frame transmitted.
0000
090
SADB_Aging
FBFLT
9
SADB Aging Period in Seconds (initial 300 decimal).
12C
092
FILTer_Control
FBFLT
8
Enable SADB, UDLT filtering.
07
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